An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Non Classical Design in MOSFETs for Improving OTA gain-bandwidth trade off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .

Recruitment bias and clinical characterstics of participants with severe cerebral palsy in a cross-sectional survey

Aim.  This article is a report of recruitment bias in a sample of 5–25-year-old patients with severe cerebral palsy.

Background.  The way in which study participants are recruited into research can be a source of bias.

Method.  A cross-sectional survey of 5–25-year-old patients with severe cerebral palsy using standardized questionnaires with parents/carers was undertaken in 2007/2008. A case register was used as the sampling frame, and 260 families were approached: 178/260 (68%) responded and 82/260 families never replied (non-respondents). Among responders: 127/178 (71%) opted in to the study, but only 123/127 were assessed, and 82/178 were opted out (or refused). Multivariable logistic regression giving odds ratios was used to study the association between participant characteristics and study outcomes (responders vs. non-responders; opting in vs. opting out; assessed vs. eligible, but not assessed).

Results.  Responders (compared with non-responders) were significantly more likely to have a family member with cerebral palsy who was male and resident in more affluent areas. Families who opted in (compared with those opting out and refusing) were more likely to have a family member with cerebral palsy and intellectual impairment and to reside in certain geographical areas. Families who were actually assessed (compared with all eligible, but not assessed) were more likely to have a family member with cerebral palsy and intellectual impairment.

Conclusion.  Several sources of bias were identified during recruitment for this study. This has implications for the interpretation and conclusions of surveys of people with disabilities and complex needs.

Voltage-activated currents in cardiac myocytes of the blue mussel, Mytilus edulis

Voltage-sensitive ionic currents were identified and characterised in ventricular myocytes of the bivalve mollusc, Mytilus edulis, using the whole-cell patch-clamp technique. Two outward currents could be distinguished. A potassium A current (I-A) activated at - 30 mV from a holding potential of - 60 mV. This transient current was inactivated by holding the cells at a potential of - 40 mV and was also blocked by applying 4-aminopyridine (3 mM) to the external bath solution. A second current was identified as a delayed rectifier (I-K). This also activated at - 30 mV but exhibited a sustained time course and was still activated at a holding potential of - 40 mV. Both outward currents were reduced in the presence of tetraethylammonium ions (30 mM). A small number of heart cells also showed an inward sodium current (I-Na). This current appeared at potentials more positive than - 50 mV, reached a maximum at - 20 mV, and decreased with further depolarisation. I-Na was inactivated at a holding potential of - 40 mV and was blocked by tetrodotoxin (1 mu M). A second inward current had a sustained time course and was not inactivated by holding the cell at a potential of -40 mV, and was also not abolished by tetrodotoxin. This current peaked at 0 mV, decreasing with further depolarisation. Furthermore, it was enhanced by the addition of barium ions (3 mM) to the bath and was blocked by external cobalt (2 mM) or nifedipine (15 mu M) These findings are consistent with this being an L-type calcium current (I-Ca) The possible physiological roles of these currents in M. edulis heart are discussed. (C) 1999 Elsevier Science Inc. All rights reserved.

Immunohistochemical localization of a Shaker-related voltage-gated potassium channel protein in Schistosoma mansoni (Trematoda: Digenea)

We have recently isolated a cDNA (SKV1.1) encoding a Shakei-related K+ channel from the human parasitic trematode Schistosoma mansoni. In order to better understand the functions of SKv1.1 protein, the distribution of SKv1.1 protein in adult S. mansoni was analyzed by immunohistochemistry using a region-specific antibody. SKV1.1 proteins were widely expressed in the nervous and muscular systems. The strongest immunoreactivity (IR) was observed in the nervous system of both male and female. In the nervous system, IR for SKv1.1 proteins was localized in cell bodies and nerve fibers of the anterior ganglia, the central commissure, and the main nerve cords. IR was also observed in the dorsal and the ventral peripheral nerve nets, fine nerve fibers entering into a variety of structures such as the dorsal tubercles, longitudinal and ventral muscle fibers, and oral and ventral suckers. In the muscular system, SKv1.1 proteins were localized to the longitudinal, circular, and ventral muscle fibers of male as well as in isolated muscle fibers where native A-type K+ currents were measured. Moderate IR was also seen in a large number of cell bodies in the parenchyma. These results indicate that SKv1.1 protein may play an important role in the regulation of the excitability of neurons and muscle cells of S. mansoni. (C) 1995 Academic Press, Inc.