Digital Elevation Models and GIS for watershed modelling and flood prediction - A case study of Accra Ghana

Geographical Information Systems (GIS) and Digital Elevation Models (DEM) can be used to perform many geospatial and hydrological modelling including drainage and watershed delineation, flood prediction and physical development studies of urban and rural settlements. This paper explores the use of contour data and planimetric features extracted from topographic maps to derive digital elevation models (DEMs) for watershed delineation and flood impact analysis (for emergency preparedness) of part of Accra, Ghana in a GIS environment. In the study two categories of DEMs were developed with 5 m contour and planimetric topographic data; bare earth DEM and built environment DEM. These derived DEMs were used as terrain inputs for performing spatial analysis and obtaining derivative products. The generated DEMs were used to delineate drainage patterns and watershed of the study area using ArcGIS desktop and its ArcHydro extension tool from Environmental Systems Research Institute (ESRI). A vector-based approach was used to derive inundation areas at various flood levels. The DEM of built-up areas was used as inputs for determining properties which will be inundated in a flood event and subsequently generating flood inundation maps. The resulting inundation maps show that about 80% areas which have perennially experienced extensive flooding in the city falls within the predicted flood extent. This approach can therefore provide a simplified means of predicting the extent of inundation during flood events for emergency action especially in less developed economies where sophisticated technologies and expertise are hard to come by. © Springer Science + Business Media B.V. 2009.

80 GSPS photonic analogue to digital conversion system using broadband continuous wave source

An 80 GSPS photonic ADC system is demonstrated, using broadband MLL and dispersive fibre to form a continuous waveform with time-wavelength mapping, and AWG to channelise. Tests are carried out for RF signals up to 10GHz. © 2005 Optical Society of America.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Crosstalk analysis of a fiber laser sensor array system based on digital phase-generated carrier scheme

A detailed study on analyzing the crosstalk in a wavelength division multiplexed fiber laser sensor array system based on a digital phase generated carrier interferometric interrogation scheme is reported. The crosstalk effects induced by the limited optical channel isolation of a dense wavelength division demultiplexer (DWDM) are presented, and the necessary channel isolation to keep the crosstalk negligible to the output signal was calculated via Bessel function expansion and demonstrated by a two serial fiber laser sensors system. Finally, a three-element fiber laser sensor array system with a 50-dB channel-isolation DWDM was built up. Experimental results demonstrated that there was no measurable crosstalk between the output channels.

Analog computation using quantum-dot cell network

A novel analog-computation system using a quantum-dot cell network is proposed to solve complex problems. Analog computation is a promising method for solving a mathematical problem by using a physical system analogous to the problem. We designed a novel quantum-dot cell consisting of three-stacked. quantum dots and constructed a cell network utilizing the nearest-neighbor interactions between the cells. We then mapped a graph 3-colorability problem onto the network so that the single-electron configuration of the network in the ground state corresponded to one of the solutions. We calculated the ground state of the cell network and found solutions to the problems. The results demonstrate that analog computation is a promising approach for solving complex problems.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Fabrication of a novel silica PLC hybrid integrated triplexer

A new-style silica planar lightwave circuit (PLC) hybrid integrated triplexer, which can demultiplex 1490-nm download data and 1550-nm download analog signals, as well as transmit 1310-nm upload data, is presented. It combines SiO2 arrayed waveguide gratings (AWGs) with integrated photodetectors (PDs) and a high performance laser diode (LD). The SiO2 AWGs realize the three-wavelength coarse wavelength-division multiplexing (CWDM). The crosstalk is less than 40 dB between the 1490- and 1550-nm channels, and less than 45 dB between 1310- and 1490- or 1550-nm channels. For the static performances of the integrated triplexer, its upload output power is 0.4 mW, and the download output photo-generated current is 76 A. In the small-signal measurement, the upstream 3-dB bandwidth of the triplexer is 4 GHz, while the downstream 3-dB bandwidths of both the analog and digital sections reach 1.9 GHz.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A New Method to Investigate InGaAsP Single-Photon Avalanche Diodes Using a Digital Sampling Oscilloscope

A near-infrared single-photon detection system is established by using pigtailed InGaAs/InP avalanche photodiodes. With a 50GHz digital sampling oscilloscope, the function and process of gated-mode (Geiger-mode) single-photon detection are intuitionally demonstrated for the first time. The performance of the detector as a gated-mode single-photon counter at wavelengths of 1310 and 1550nm is investigated. At the operation temperature of 203K,a quantum efficiency of 52% with a dark count probability per gate of 2. 4 * 10~(-3), and a gate pulse repetition rate of 50kHz are obtained at 1550nm. The corresponding parameters are 43% , 8. 5 * 10~(-3), and 200kHz at 238K.