Application of UPFC for system security improvement under normal and network contingencies

Electric power systems are exposed to various contingencies. Network contingencies often contribute to over-loading of network branches, unsatisfactory voltages and also leading to problems of stability/voltage collapse. To maintain security of the systems, it is desirable to estimate the effect of contingencies and plan suitable measures to improve system security/stability. This paper presents an approach for selection of unified power flow controller (UPFC) suitable locations considering normal and network contingencies after evaluating the degree of severity of the contingencies. The ranking is evaluated using composite criteria based fuzzy logic for eliminating masking effect. The fuzzy approach, in addition to real power loadings and bus voltage violations, voltage stability indices at the load buses also used as the post-contingent quantities to evaluate the network contingency ranking. The selection of UPFC suitable locations uses the criteria on the basis of improved system security/stability. The proposed approach for selection of UPFC suitable locations has been tested under simulated conditions on a few power systems and the results for a 24-node real-life equivalent EHV power network and 39-node New England (modified) test system are presented for illustration purposes.

Artificial neural network application to power system voltage stability improvement

As power systems grow in their size and interconnections, their complexity increases. Rising costs due to inflation and increased environmental concerns has made transmission, as well as generation systems be operated closer to design limits. Hence power system voltage stability and voltage control are emerging as major problems in the day-to-day operation of stressed power systems. For secure operation and control of power systems under normal and contingency conditions it is essential to provide solutions in real time to the operator in energy control center (ECC). Artificial neural networks (ANN) are emerging as an artificial intelligence tool, which give fast, though approximate, but acceptable solutions in real time as they mostly use the parallel processing technique for computation. The solutions thus obtained can be used as a guide by the operator in ECC for power system control. This paper deals with development of an ANN architecture, which provide solutions for monitoring, and control of voltage stability in the day-to-day operation of power systems.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Effect of Interfacial Microstructure of Adsorbed Poly(ethylene glycol) Monooleate on Steel Substrate on Sliding Friction in Oil in Water Emulsion

The concentration of a nonionic surfactant and water pH were varied in an oil-in-water emulsion to minimize the friction coefficient between a steel ball sliding on a steel flat. At a surfactant concentration near the CMC (critical micelle concentration) the oil droplet size was found to be minimum. In this paper we study the microstructure of the surfactant molecules self-assembled on the steel substrate in water to comment on the ability of the surfactant aggregate to attract and retain oil. We find that a near semicylindrical hemimiceller microstructure with hydrocarbon tails projecting into bulk water as obtained at CMC in near neutral water is best able to capture and retain oil in yielding a low coefficient of friction.

Decentralized linear quadratic power system stabilizers for multi-machine power systems

Linear quadratic stabilizers are well-known for their superior control capabilities when compared to the conventional lead-lag power system stabilizers. However, they have not seen much of practical importance as the state variables are generally not measurable; especially the generator rotor angle measurement is not available in most of the power plants. Full state feedback controllers require feedback of other machine states in a multi-machine power system and necessitate block diagonal structure constraints for decentralized implementation. This paper investigates the design of Linear Quadratic Power System Stabilizers using a recently proposed modified Heffron-Phillip's model. This model is derived by taking the secondary bus voltage of the step-up transformer as reference instead of the infinite bus. The state variables of this model can be obtained by local measurements. This model allows a coordinated linear quadratic control design in multi machine systems. The performance of the proposed controller has been evaluated on two widely used multi-machine power systems, 4 generator 10 bus and 10 generator 39 bus systems. It has been observed that the performance of the proposed controller is superior to that of the conventional Power System Stabilizers (PSS) over a wide range of operating and system conditions.

A generalized geo-hazard warning system

An automated geo-hazard warning system is the need of the hour. It is integration of automation in hazard evaluation and warning communication. The primary objective of this paper is to explain a geo-hazard warning system based on Internet-resident concept and available cellular mobile infrastructure that makes use of geo-spatial data. The functionality of the system is modular in architecture having input, understanding, expert, output and warning modules. Thus, the system provides flexibility in integration between different types of hazard evaluation and communication systems leading to a generalized hazard warning system. The developed system has been validated for landslide hazard in Indian conditions. It has been realized through utilization of landslide causative factors, rainfall forecast from NASA's TRMM (Tropical Rainfall Measuring Mission) and knowledge base of landslide hazard intensity map and invokes the warning as warranted. The system evaluated hazard commensurate with expert evaluation within 5-6 % variability, and the warning message permeability has been found to be virtually instantaneous, with a maximum time lag recorded as 50 s, minimum of 10 s. So it could be concluded that a novel and stand-alone system for dynamic hazard warning has been developed and implemented. Such a handy system could be very useful in a densely populated country where people are unaware of the impending hazard.

Switching of a Sixteen Electrode Array for Wireless EIT System Using a RF-Based 8-Bit Digital Data Transmission Technique

Surface electrode switching of 16-electrode wireless EIT is studied using a Radio Frequency (RF) based digital data transmission technique operating with 8 channel encoder/decoder ICs. An electrode switching module is developed the analog multiplexers and switched with 8-bit parallel digital data transferred by transmitter/receiver module developed with radio frequency technology. 8-bit parallel digital data collected from the receiver module are converted to 16-bit digital data by using binary adder circuits and then used for switching the electrodes in opposite current injection protocol. 8-bit parallel digital data are generated using NI USB 6251 DAQ card in LabVIEW software and sent to the transmission module which transmits the digital data bits to the receiver end. Receiver module supplies the parallel digital bits to the binary adder circuits and adder circuit outputs are fed to the multiplexers of the electrode switching module for surface electrode switching. 1 mA, 50 kHz sinusoidal constant current is injected at the phantom boundary using opposite current injection protocol. The boundary potentials developed at the voltage electrodes are measured and studied to assess the wireless data transmission.

Increasing System Capacity in Uplink Multiuser MIMO Using Sparsity Exploiting Receiver

In multiuser communication on the uplink, all subscribed users may not be active simultaneously. This leads to sparsity in the activity pattern in the users' transmissions, which can be exploited in the multiuser MIMO receiver at the base station (BS). Because of no transmissions from inactive users, joint detection at the BS has to consider an augmented signal set that includes zero. In this paper, we propose a receiver that exploits this inactivity-induced sparsity and considers the zero-augmented signal set. The proposed receiver is based on Markov Chain Monte Carlo techniques. Near-optimal performance and increased system capacity (in terms of number of users in the system) are demonstrated. For example, a multiuser MIMO system with N = 32 receive antennas at the BS and an user activity factor of 0.2 supports 51 uplink users meeting a QoS of 10(-3) coded bit error rate.

A scalable network port scan detection system on FPGA

With ever increasing network speed, scalable and reliable detection of network port scans has become a major challenge. In this paper, we present a scalable and flexible architecture and a novel algorithm, to detect and block port scans in real time. The proposed architecture detects fast scanners as well as stealth scanners having large inter-probe periods. FPGA implementation of the proposed system gives an average throughput of 2 Gbps with a system clock frequency of 100 MHz on Xilinx Virtex-II Pro FPGA. Experimental results on real network trace show the effectiveness of the proposed system in detecting and blocking network scans with very low false positives and false negatives.

Interplay of software bloat, hardware energy proportionality and system bottlenecks

In large flexible software systems, bloat occurs in many forms, causing excess resource utilization and resource bottlenecks. This results in lost throughput and wasted joules. However, mitigating bloat is not easy; efforts are best applied where savings would be substantial. To aid this we develop an analytical model establishing the relation between bottleneck in resources, bloat, performance and power. Analyses with the model places into perspective results from the first experimental study of the power-performance implications of bloat. In the experiments we find that while bloat reduction can provide as much as 40% energy savings, the degree of impact depends on hardware and software characteristics. We confirm predictions from our model with selected results from our experimental study. Our findings show that a software-only view is inadequate when assessing the effects of bloat. The impact of bloat on physical resource usage and power should be understood for a full systems perspective to properly deploy bloat reduction solutions and reap their power-performance benefits.