A CMOS/SOI single-input PWM discriminator for low-voltage body-implanted applications

A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Low voltage electroluminescence of terbium- and thulium-doped zinc oxide films

Strong interest in developing technology for visual information. stimulates research for thin film electroluminescent devices. Here, for the first time, we report that thulium- and terbium-doped zinc-oxide films are suitable for electroluminescence applications. Two different devices were assembled as lTO/LiF/ZnO:RE/LiF/Al or ITO/SiO2/ZnO:RE/SiO2/Al, where ZnO:RE is a film of zinc oxide containing 10 at% of Tb3+ or Tm3+. Electroluminescence spectra show that besides a broad emission band with maximum around 650 nm assigned to ZnO, also emission lines from Tb3+ at 484 nm (D-5(4) -> F-7(6)), 543 nm (D-5(4) -> F-7(6)), and 589 nm (D-5(4) -> F-7(4)), or from Tm3+ at 478 nm ((1)G(4) -> H-3(6)), and 511 mn (D-1(2) -> H-3(5)) were detected. Intensity of emission as function of applied voltage and current-voltage characteristic are shown and discussed. (c) 2005 Elsevier B.V. All rights reserved.

A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to (gm)-C filters

A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.

The effect of TiO(2) on the microstructural and electrical properties of low voltage varistor based on (Sn,Ti)O(2) ceramics

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift

A new topology for a LVLP variable-gain CMOS amplifier is presented. Input- and load-stage are built around triode-transconductors so that voltage-gain is fully defined by a linear relationship involving only device-geometries and biases. Excellent gain-accuracy, temperature-insensitivity; and wide range of programmability, are thus achieved. Moreover, adaptative biasing improves the common-mode voltage stability upon gain-adjusting. As an example, a 0-40dB programmablegain audio-amplifier is designed. Its performance is supported by a range of simulations. For VDD=1.8V and 20dB-nominal gain, one has Av=19.97dB, f3db=770KHz and quiescent dissipation of 378μW. Over temperatures from -25°C to 125°C, the 0. ldB-bandwidth is 52KHz. Dynamic-range is optimized to 57.2dB and 42.6dB for gains of 20dB and 40dB, respectively. THD figures correspond to -60.6dB@Vout= 1Vpp and -79.7dB@Vout= 0.5 Vpp. A nearly constant bandwidth for different gains is also attained.

A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency

A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to 58%. Total quiescent dissipation is 260μW. A range of PSPICE simulation supports theoretical analysis. Excellent linearity is observed on dc characteristic. Assuming a ±0.5% mismatch on (W/L) and VTH THD at full-scale is 0.93% and 1.42%, for output frequencies of 1MHz and 10MHz, respectively.

A low-voltage programmable-gain current-mode amplifier

A CMOS low-voltage, wide-band continuous-time current amplifier is presented. Based on an open-loop topology, the circuit is composed by transresistance and transconductance stages built around triode-operating transistors. In addition to an extended dynamic range, the amplifier gain can be programmed within good accuracy by the rapport between the aspect-ratio of such transistors and tuning biases Vxand Vy. A balanced current-amplifier according to a single I. IV-supply and a 0.35μm fabrication process is designed. Simulated results from PSPiCE and Bsm3v3 models indicate a programmable gain within the range 20-34dB and a minimum break-frequency of IMHz @CL=IpF. For a 200 μApp-level, THD is 0.8% and 0.9% at IKHz and 100KHz, respectively. Input noise is 405pA√Hz @20dB-gain, which gives a SNR of 66dB @1MHz-bandwidth. Maximum quiescent power consumption is 56μ W. © 2002 IEEE.

An active leakage-injection scheme applied to low-voltage SRAMs

An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Evaluation of a multiobjective performance index for distribution systems with distributed generation

Here a multiobjective performance index for distribution systems with distributed generation based on a steady-state analysis of the network is proposed. This index quantifies the distributed generation impact on total losses, voltage profile and short circuit currents, and will be used as objective function in an evolutionary algorithm aimed at searching the best points for connecting distributed generators. Moreover, a loss allocation technique, based on the Zbus method, is applied on the original configuration of the network to obtain a good quality initial population. An IEEE medium voltage distribution network is analysed and results are presented and discussed.

Distribution network reconfiguration using an efficient evolutionary algorithm

Network reconfiguration is an important tool to optimize the operating conditions of a distribution system. This is accomplished modifying the network structure of distribution feeders by changing the open/close status of sectionalizing switches. This not only reduces the power losses, but also relieves the overloading of the network components. Network reconfiguration belongs to a complex family of problems because of their combinatorial nature and multiple constraints. This paper proposes a solution to this problem, using a specialized evolutionary algorithm, with a novel codification, and a brand new way of implement the genetic operators considering the problem characteristics. The algorithm is presented and tested in a real distribution system, showing excellent results and computational efficiency. © 2007 IEEE.

Distribution network planning using a constructive heuristic algorithm

An optimization technique to solve distribution network planning (DNP) problem is presented. This is a very complex mixed binary nonlinear programming problem. A constructive heuristic algorithm (CHA) aimed at obtaining an excellent quality solution for this problem is presented. In each step of the CHA, a sensitivity index is used to add a circuit or a substation to the distribution network. This sensitivity index is obtained solving the DNP problem considering the numbers of circuits and substations to be added as continuous variables (relaxed problem). The relaxed problem is a large and complex nonlinear programming and was solved through an efficient nonlinear optimization solver. A local improvement phase and a branching technique were implemented in the CHA. Results of two tests using a distribution network are presented in the paper in order to show the ability of the proposed algorithm. ©2009 IEEE.

An efficient codification to solve distribution network reconfiguration for loss reduction problem

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)