Double-gyroid morphology of a polystyrene-block-poly(ferrocenylethylmethylsilane) diblock copolymer: a route to ordered bicontinuous nanoscale architectures

A polystyrene-block-poly(ferrocenylethylmethylsilane) diblock copolymer, displaying a double-gyroid morphology when self-assembled in the solid state, has been prepared with a PFEMS volume fraction phi(PFMS)=0.39 and a total molecular weight of 64 000 Da by sequential living anionic polymerisation. A block copolymer with a metal-containing block with iron and silicon in the main chain was selected due to its plasma etch resistance compared to the organic block. Self-assembly of the diblock copolymer in the bulk showed a stable, double-gyroid morphology as characterised by TEM. SAXS confirmed that the structure belonged to the Ia3d space group.

Parallel pipelined histogram architectures

Proposed is a unique cell histogram architecture which will process k data items in parallel to compute 2q histogram bins per time step. An array of m/2q cells computes an m-bin histogram with a speed-up factor of k; k ⩾ 2 makes it faster than current dual-ported memory implementations. Furthermore, simple mechanisms for conflict-free storing of the histogram bins into an external memory array are discussed.

Parallel pipelined array architectures for real-time histogram computation in consumer devices

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle.

Parallel Architectures for High Speed Multipliers

The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.

C-slow retimed parallel histogram architectures for consumer imaging devices

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

On modeling and evaluating multicomputer transcoding architectures for live-video streams

The pervasive and ubiquitous computing has motivated researches on multimedia adaptation which aims at matching the video quality to the user needs and device restrictions. This technique has a high computational cost which needs to be studied and estimated when designing architectures and applications. This paper presents an analytical model to quantify these video transcoding costs in a hardware independent way. The model was used to analyze the impact of transcoding delays in end-to-end live-video transmissions over LANs, MANs and WANs. Experiments confirm that the proposed model helps to define the best transcoding architecture for different scenarios.

Enzyme immobilisation on electroactive nanostructured membranes (ENM): Optimised architectures for biosensing

Electroactive nanostructured membranes have been produced by the layer-by-layer (LbL) technique, and used to make electrochemical enzyme biosensors for glucose by modification with cobalt hexacyanoferrate redox mediator and immobilisation of glucose oxidase enzyme. Indium tin oxide (ITO) glass electrodes were modified with up to three bilayers of polyamidoamine (PAMAM) dendrimers containing gold nanoparticles and poly(vinylsulfonate) (PVS). The gold nanoparticles were covered with cobalt hexacyanoferrate that functioned as a redox mediator, allowing the modified electrode to be used to detect H(2)O(2), the product of the oxidase enzymatic reaction, at 0.0 V vs. SCE. Enzyme was then immobilised by cross-linking with glutaraldehyde. Several parameters for optimisation of the glucose biosensor were investigated, including the number of deposited bilayers, the enzyme immobilisation protocol and the concentrations of immobilised enzyme and of the protein that was crosslinked with PAMAM. The latter was used to provide glucose oxidase with a friendly environment, in order to preserve its bioactivity. The optimised biosensor, with three bilayers, has high sensitivity and operational stability, with a detection limit of 6.1 mu M and an apparent Michaelis-Menten constant of 0.20 mM. It showed good selectivity against interferents and is suitable for glucose measurements in natural samples. (C) 2008 Elsevier B.V. All rights reserved.

The CATH classification revisited-architectures reviewed and new ways to characterize structural divergence in superfamilies

The latest version of CATH (class, architecture, topology, homology) (version 3.2), released in July 2008 (http://www.cathdb.info), contains 1 14215 domains, 2178 Homologous superfamilies and 1110 fold groups. We have assigned 20 330 new domains, 87 new homologous superfamilies and 26 new folds since CATH release version 3.1. A total of 28 064 new domains have been assigned since our NAR 2007 database publication (CATH version 3.0). The CATH website has been completely redesigned and includes more comprehensive documentation. We have revisited the CATH architecture level as part of the development of a `Protein Chart` and present information on the population of each architecture. The CATHEDRAL structure comparison algorithm has been improved and used to characterize structural diversity in CATH superfamilies and structural overlaps between superfamilies. Although the majority of superfamilies in CATH are not structurally diverse and do not overlap significantly with other superfamilies, similar to 4% of superfamilies are very diverse and these are the superfamilies that are most highly populated in both the PDB and in the genomes. Information on the degree of structural diversity in each superfamily and structural overlaps between superfamilies can now be downloaded from the CATH website.

Studies of Design and Assembly Defects on Integrated and Modular Architectures

It is known that despite companies’ efforts to improve the quality of their products, design and assembly defects results in large repair costs both in terms of repair and providing feedback to the origin of the defect. The purpose of this paper is to study these types of defects and the defect rates in design and assembly. The paper presents a web based questionnaire answered by 29 companies. The result shows that the defect rate (defects per product) spanned from 0.01 to 10. Also, design and assembly defects covered 46%, 23% respectively, of all occurred defects. A case study is also presented, performed at a company who recently implemented a modular architecture. In this company, defects from 5 700 integrated product architectures are compared with defects from 431 modular architectures. The average defect rate increased by 21.5% – from 0.65 to 0.79 – when a more modular architecture has been implemented. Furthermore, the study showed that the assembly defects have decreased while the design defects increased. The results presented in this paper will also support the development of the MPV (Module Property Verification) method which is briefly described.

Module property verification : A method to plan and perform quality verifications in modular architectures

Modular product architectures have generated numerous benefits for companies in terms of cost, lead-time and quality. The defined interfaces and the module’s properties decrease the effort to develop new product variants, and provide an opportunity to perform parallel tasks in design, manufacturing and assembly. The background of this thesis is that companies perform verifications (tests, inspections and controls) of products late, when most of the parts have been assembled. This extends the lead-time to delivery and ruins benefits from a modular product architecture; specifically when the verifications are extensive and the frequency of detected defects is high. Due to the number of product variants obtained from the modular product architecture, verifications must handle a wide range of equipment, instructions and goal values to ensure that high quality products can be delivered. As a result, the total benefits from a modular product architecture are difficult to achieve. This thesis describes a method for planning and performing verifications within a modular product architecture. The method supports companies by utilizing the defined modules for verifications already at module level, so called MPV (Module Property Verification). With MPV, defects are detected at an earlier point, compared to verification of a complete product, and the number of verifications is decreased. The MPV method is built up of three phases. In Phase A, candidate modules are evaluated on the basis of costs and lead-time of the verifications and the repair of defects. An MPV-index is obtained which quantifies the module and indicates if the module should be verified at product level or by MPV. In Phase B, the interface interaction between the modules is evaluated, as well as the distribution of properties among the modules. The purpose is to evaluate the extent to which supplementary verifications at product level is needed. Phase C supports a selection of the final verification strategy. The cost and lead-time for the supplementary verifications are considered together with the results from Phase A and B. The MPV method is based on a set of qualitative and quantitative measures and tools which provide an overview and support the achievement of cost and time efficient company specific verifications. A practical application in industry shows how the MPV method can be used, and the subsequent benefits

Transparent Fault Tolerance for Web Services based Architectures

Service-based architectures enable the development of new classes of Grid and distributed applications. One of the main capabilities provided by such systems is the dynamic and flexible integration of services, according to which services are allowed to be a part of more than one distributed system and simultaneously serve different applications. This increased flexibility in system composition makes it difficult to address classical distributed system issues such as fault-tolerance. While it is relatively easy to make an individual service fault-tolerant, improving fault-tolerance of services collaborating in multiple application scenarios is a challenging task. In this paper, we look at the issue of developing fault-tolerant service-based distributed systems, and propose an infrastructure to implement fault tolerance capabilities transparent to services.