Metal catalysis-free, direction-controlled planar growth of single-crystalline alpha-Si3N4 nanowires on Si(100) substrate

Single-crystalline alpha-Si3N4 nanowires are controlled to grow perpendicular to the wet-etched trenches in the SiO0.94 film on the plane of the Si substrate without metal catalysis. A detailed characterization is carried out by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). The photoluminescence at 600 nm from alpha-Si3N4 nanowires is attributed to the recombination at the defect state formed by the Si dangling bond N3 equivalent to Si-center dot. The growth mechanism is considered to be related to the catalysis and nitridation of SiO nanoclusters preferably re-deposited around the inner corner of the trenches, as well as faster Si diffusion along the slanting side walls of the trenches. This simple direction-controlled growth method is compatible with the CMOS process, and could facilitate the fabrication of alpha-Si3N4 nanoelectronic or nanophotonic devices on the Si platform.

Green-light-emitting ZnSe nanowires fabricated via vapor phase growth

Stoichiometric ZnSe nanowires have been synthesized through a vapor phase reaction of zinc and selenium powder on the (100) silicon substrate coated with a gold film of 2 nm in thickness. The microstructures and the chemical compositions of the as-grown nanowires have been investigated by means of electron microscopy, the energy dispersive spectroscopy, and Raman spectroscopy. The results reveal that the as-grown materials consist of ZnSe nanowires with diameters ranging from 5 to 50 nm. Photoluminescence of the sample demonstrates a strong green emission from room temperature down to 10 K. This is attributed to the recombination of electrons from conduction band to the medium deep Au acceptors. (C) 2003 American Institute of Physics.

Experimental Study on the Subthreshold Swing of Silicon Nanowire Transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I-ON) and off-current (I-OFF) of the fabricated silicon nanowire FET are 0.59 mu A and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mVN respectively due to the 30 nm thick gate oxide and 1015 cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Synthesis & characterisation of group IV semiconducting nanowires

Semiconductor nanowires, particularly group 14 semiconductor nanowires, have been the subject of intensive research in the recent past. They have been demonstrated to provide an effective, versatile route towards the continued miniaturisation and improvement of microelectronics. This thesis aims to highlight some novel ways of fabricating and controlling various aspects of the growth of Si and Ge nanowires. Chapter 1 highlights the primary technique used for the growth of nanowires in this study, namely, supercritical fluid (SCF) growth reactions. The advantages (and disadvantages) of this technique for the growth of Si and Ge nanowires are highlighted, citing numerous examples from the past ten years. The many variables involved in this technique are discussed along with the resultant characteristics of nanowires produced (diameter, doping, orientation etc.). Chapter 2 outlines the experimental methodologies used in this thesis. The analytical techniques used for the structural characterisation of nanowires produced are also described as well as the techniques used for the chemical analysis of various surface terminations. Chapter 3 describes the controlled self-seeded growth of highly crystalline Ge nanowires, in the absence of conventional metal seed catalysts, using a variety of oligosilylgermane precursors and mixtures of germane and silane compounds. A model is presented which describes the main stages of self-seeded Ge nanowire growth (nucleation, coalescence and Ostwald ripening) from the oligosilylgermane precursors and in conjunction with TEM analysis, a mechanism of growth is proposed. Chapter 4 introduces the metal assisted etching (MAE) of Si substrates to produce Si nanowires. A single step metal-assisted etch (MAE) process, utilising metal ion-containing HF solutions in the absence of an external oxidant, was developed to generate heterostructured Si nanowires with controllable porous (isotropically etched) and non-porous (anisotropically etched) segments. In Chapter 5 the bottom-up growth of Ge nanowires, similar to that described in Chapter 3, and the top down etching of Si, described in Chapter 4, are combined. The introduction of a MAE processing step in order to “sink” the Ag seeds into the growth substrate, prior to nanowire growth, is shown to dramatically decrease the mean nanowire diameters and to narrow the diameter distributions. Finally, in Chapter 6, the biotin – streptavidin interaction was explored for the purposes of developing a novel Si junctionless nanowire transistor (JNT) sensor.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Multiple self-aligned iron nanowires by a dual selective chemical vapor deposition process

We have demonstrated a self-aligned process to fabricate organized iron nanowires on a planarized surface with wire dimensions down to 50 nm. Polishing was used to expose an alternating silicon silicon dioxide edge and a dual selective metal deposition process produced the nanowires. The initial selective deposition produced a tungsten layer on the exposed polysilicon regions. The discovery that selective chemical vapor deposition of iron from Fe(CO)(5) precursor on dielectric surfaces over tungsten surfaces is the key factor that enables the self-alignment of the iron nanowires. Dimensions of the wires are determined by the thickness of the thermal oxide. (c) 2007 The Electrochemical Society.

Oblique Angle Deposition of Germanium Film on Silicon Substrate

The effect of flux angle, substrate temperature and deposition rate on obliquely deposited germanium (Ge) films has been investigated. By carrying out deposition with the vapor flux inclined at 87° to the substrate normal at substrate temperatures of 250°C or 300°C, it may be possible to obtain isolated Ge nanowires. The Ge nanowires are crystalline as shown by Raman Spectroscopy.

Boron carbide nanowires with uniform CNχ coatings

Boron carbide nanowires with uniform carbon nitride coating layers were synthesized on a silicon substrate using a simple thermal process. The structure and morphology of the as-synthesized nanowires were characterized using x-ray diffraction, scanning and transmission electron microscopy and electron energy loss spectroscopy. A correlation between the surface smoothness of the nanowire sidewalls and their lateral sizes has been observed and it is a consequence of the anisotropic formation of the coating layers. A growth mechanism is also proposed for these growth phenomena.

Fluoride-assisted synthesis of mullite (Al5.65 Si0.35 O9.175) nanowires

Novel silicon-deficient mullite (Al_5.65Si_0.35O_9.175) single crystal nanowires were synthesized in large quantities on mica substrates assisted by the intermediate fluoride species. The nanowires have diameters in the range 50–100 nm and typical lengths of several µm. Aligned nanowires were observed at the substrate edge. The nanowires have strong photoluminescence (PL) emission bands at 310, 397, 452 and 468 nm.

Selective oxidation synthesis of MnCr2O4 spinel nanowires from Commercial stainless steel foil

For the first time, MnCr₂O₄ spinel single-crystalline nanowires were simply synthesized by heating commercial stainless steel foil (Cr_0.19Fe_0.70Ni_0.11) under a reducing atmosphere. The nanowires have an average diameter of 50 nm and a length of about 10 μm. Some nanowires are sheathed with a thin layer of amorphous silicon oxide. Photoluminescence measurements revealed that the nanowires exhibit an emission band at 435 nm, which resulted from the oxygen-related defects in the silicon oxide sheath. It was found that the reducing atmosphere plays a key role for the nanowire growth. In the reducing atmosphere, the Mn and Cr elements in the stainless steel could be selectively oxidized because of their higher affinity for oxygen than the Fe and Ni elements. The Fe and Ni elements in the stainless steel, however, acted as the catalyst for the vapor–liquid–solid (VLS) growth of the MnCr₂O₄ nanowires.

Plasma-assisted self-catalytic vapour-liquid-solid growth of β-SiC nanowires

Long and straight β-SiC nanowires are synthesized via the direct current arc discharge method with a mixture of silicon, graphite and silicon dioxide as the precursor. Detailed investigations with x-ray diffraction, scanning electron microscopy, energy dispersive x-ray spectroscopy, Raman scattering spectroscopy, transmission electron microscopy and selected area electron diffraction confirm that the β-SiC nanowires, which are about 100–200 nm in stem diameter and 10–20 µm in length, consist of a solid single-crystalline core along the (1 1 1) direction wrapped with an amorphous SiO_x layer. A broad photoluminescence emission peak with a maximum at about 336 nm is observed at room temperature. A direct current arc plasma-assisted self-catalytic vapour–liquid–solid process is proposed as the growth mechanism of the β-SiC nanowires. This synthesis technique is capable of producing SiC nanowires free of metal contamination with a preferential growth direction and a high aspect ratio, without the designed addition of transition metals as catalysts.

Synthesis and characterization of tin dioxide core-shell structure nanowires

In this study, one-dimensional and quasi-one-dimensional tin dioxide nanowires and nan-owalls were fabricated by the use of the chemical vapor deposition technique. It was demonstrated that the growth and nanostructure of tin oxide can be controlled by varying the thickness of gold layer and the partial pressure of vapor at growing sites. Nanowires with a core-shell structure, i.e., pure tin core and tin oxide shell, were synthesized from C-S_nO₂ powders at a mol ratio of C/S_nO₂=3/5 on both silicon and Lanthanum Strontium Co-balt Ferrite ceramic wafers through the vapor-solid mechanism. The conditions that are favorable to the growth of core-shell structure nanowires are investigated.

Effect of processing conditions on the nucleation and growth of indium-tin-oxide nanowires made by pulsed laser ablation

Indium-tin oxide nanowires were deposited by excimer laser ablation onto catalyst-free oxidized silicon substrates at a low temperature of 500 degrees C in a nitrogen atmosphere. The nanowires have branches with spheres at the tips, indicating a vapor-liquid-solid (VLS) growth. The deposition time and pressure have a strong influence on the areal density and length of the nanowires. At the earlier stages of growth, lower pressures promote a larger number of nucleation centers. With the increase in deposition time, both the number and length of the wires increase up to an areal density of about 70 wires/mu m(2). After this point all the material arriving at the substrate is used for lengthening the existing wires and their branches. The nanowires present the single-crystalline cubic bixbyite structure of indium oxide, oriented in the [100] direction. These structures have potential applications in electrical and optical nanoscale devices.

Scaled down physical properties of semiconductor nanowires for nanoelectronics scaling up

Semiconductor nanowires (NWs) are one- or quasi one-dimensional systems whose physical properties are unique as compared to bulk materials because of their nanoscaled sizes. They bring together quantum world and semiconductor devices. NWs-based technologies may achieve an impact comparable to that of current microelectronic devices if new challenges will be faced. This thesis primarily focuses on two different, cutting-edge aspects of research over semiconductor NW arrays as pivotal components of NW-based devices. The first part deals with the characterization of electrically active defects in NWs. It has been elaborated the set-up of a general procedure which enables to employ Deep Level Transient Spectroscopy (DLTS) to probe NW arrays’ defects. This procedure has been applied to perform the characterization of a specific system, i.e. Reactive Ion Etched (RIE) silicon NW arrays-based Schottky barrier diodes. This study has allowed to shed light over how and if growth conditions introduce defects in RIE processed silicon NWs. The second part of this thesis concerns the bowing induced by electron beam and the subsequent clustering of gallium arsenide NWs. After a justified rejection of the mechanisms previously reported in literature, an original interpretation of the electron beam induced bending has been illustrated. Moreover, this thesis has successfully interpreted the formation of NW clusters in the framework of the lateral collapse of fibrillar structures. These latter are both idealized models and actual artificial structures used to study and to mimic the adhesion properties of natural surfaces in lizards and insects (Gecko effect). Our conclusion are that mechanical and surface properties of the NWs, together with the geometry of the NW arrays, play a key role in their post-growth alignment. The same parameters open, then, to the benign possibility of locally engineering NW arrays in micro- and macro-templates.