Design and Performance Analysis of a 2.5 MW-Class HTS Synchronous Motor for Ship Propulsion

The development of cryogenic technology and high temperature superconducting (HTS) materials has seen continued interest worldwide in the development of HTS machines since the late 1980s. In this paper, the authors present a conceptual design of a 2.5 MW class synchronous motor. The structure of the motor is specified and the motor performance is analyzed via a three-dimensional model using the finite element method (FEM). Rotor optimization is carried out to decrease the harmonic components in the air gap field generated by HTS tapes. Based on the results of this 3D simulation, the determination of the operating conditions and load angle is discussed with consideration to the HTS material properties. The economic viability of air-core and iron-core designs is compared. The results show that this type of HTS machine has the potential to achieve an economic, efficient and effective machine design, which operates at a low load angle, and this design process provides a practical way to simulate and analyze the performance of such machines.

Performance analysis and testing of a 250 kW medium-speed brushless doubly-fed induction generator

This study presents the performance analysis and testing of a 250 kW medium-speed brushless doubly-fed induction generator (DFIG), and its associated power electronics and control systems. The experimental tests confirm the design, and showthe system's steady-state and dynamic performance and grid low-voltage ride- through capability. The medium-speed brushless DFIG in combination with a simplified two-stage gearbox promises a low-cost low-maintenance and reliable drivetrain for wind turbine applications. © The Institution of Engineering and Technology 2013.

Design and performance analysis of a 6 MW medium-speed Brushless DFIG

The paper presents the design and performance analysis of a 6 MW medium-speed Brushless Doubly-Fed Induction Generation (Brushless DFIG) for a wind turbine drivetrain. Two machines with different frame sizes have been designed to show the flexibility of the design procedure. The mediumspeed Brushless DFIG in combination with a two stage gearbox offers a low-cost, low-maintenance and reliable drivetrain for wind turbine applications.

Performance analysis of very-small-aperture lasers

The fabrication of very-small-aperture lasers is demonstrated, and their performance is analyzed. Because of strong optical feedback caused by a gold film on the front facet of the laser, its behavior changes: The threshold current decreases, the density of light inside the laser diode and the redshift effect of the spectra are enhanced, and the laser diode's lifetime is shorter than that of common laser diodes with large driving current. (c) 2005 Optical Society of America

On the performance analysis and design of a novel shared-layer integrated devices using RCE-p-i-n-PD/SHBT - art. no. 67820J

We have explored the shared-layer integration fabrication of an resonant-cavity-enhanced p-i-n photodector (RCE- p-i-n-PD) and a single heterojunction bipolar transistor (SHBT) with the same epitaxy grown layer structure. MOCVD growth of the different layer structure for the GaAs based RCE- p-i-n-PD/SHBT require compromises to obtain the best performance of the integrated devices. The SHBT is proposed with super-lattice in the collector, and the structure of the base and the collector of the SHBT is used for the RCE. Up to now, the DC characteristics of the integrated device have been obtained.

Comprehensive performance analysis of popular odd-symmetric phase masks used for wave-front coded imaging system

(973 Program）No.2009CB724006.

Modification of a poly(methyl methacrylate) injection-molded microchip and its use for high performance analysis of DNA

Inexpensive and permanently modified poly(methyl methacrylate)(PMMA) microchips were fabricated by an injection-molding process. A novel sealing method for plastic microchips at room temperature was introduced. Run-to-run and chip-to-chip reproducibility was good, with relative standard deviation values between 1-3% for the run-to-run and less than 2.1% for the chip-to-chip comparisons. Acrylonitrile-butadiene-styrene (ABS) was used as an additive in PMMA substrates. The proportions of PMMA and ABS were optimized. ABS may be considered as a modifier, which obviously improved some characteristics of the microchip, such as the hydrophilicity and the electro-osmotic flow (EOF). The detection limit of Rhodamine 6G dye for the modified microchip on the home-made microchip analyzer showed a dramatic 100-fold improvement over that for the unmodified PMMA chip. A detection limit of the order of 10(-20) mole has been achieved for each injected phiX-174/HaeIII DNA fragment with the baseline separation between 271 and 281 bp, and fast separation of 11 DNA restriction fragments within 180 seconds. Analysis of a PCR product from the tobacco ACT gene was performed on the modified microchip as an application example.

Performance Analysis of a WWW Server

This paper addresses the problem of analyzing performance of WWW servers. The web has experienced a phenomenal growth and has become the most popular Internet application. As a consequence of its large popularity, the Internet has suffered from various performance problems, such as network congestion and overloaded servers. These days, it is not uncommon to find servers refusing connections because they are overloaded. Performance has always been a key issue in the design and operation of on-line systems. With regard to Internet, performance is also critical, because users want fast and easy access to all objects (i.e., documents, pictures, audio, and video) available on the net. Thus, it is important to understand WWW performance issues. This paper focuses on the performance analysis of a Web server. Using a synthetic benchmark (WebStone), we analyze three different Web server software running on top of a Windows NT platform and performing some typical WWW tasks.

Performance analysis of a register insertion ring with a variable size buffer

There has been a recent revival of interest in the register insertion (RI) protocol because of its high throughput and low delay characteristics. Several variants of the protocol have been investigated with a view to integrating voice and data applications on a single local area network (LAN). In this paper the performance of an RI ring with a variable size buffer is studied by modelling and simulation. The chief advantage of the proposed scheme is that an efficient but simple bandwidth allocation scheme is easily incorporated. Approximate formulas are derived for queue lengths, queueing times, and total end-to-end transfer delays. The results are compared with previous analyses and with simulation estimates. The effectiveness of the proposed protocol in ensuring fairness of access under conditions of heavy and unequal loading is investigated.