Projeto Vidas Paralelas: estudo sobre uma experiência de participação em saúde do trabalhador no Rio de Janeiro

O objeto deste estudo é o Projeto Vidas Pararelas (PVP) no estado do Rio de Janeiro. Possui como objetivo geral estudar a experiência do PVP do Rio de Janeiro à luz dos conceitos da Educação Popular e Saúde (EPS). Como norteador da pesquisa, utilizamos o método qualitativo e para a análise dos dados, utilizamos a análise de conteúdo. O cenário da pesquisa consta de tudo que envolve o PVP, seus integrantes e o ambiente virtual. Antes de apresentarmos os resultados das entrevistas, descrevemos o componente digital do PVP (o site) e o perfil dos sujeitos da pesquisa que foi composta de 11 trabalhadores inseridos no PVP RJ. Categorizamos os achados das entrevistas em quatro tópicos: o primeiro, fala sobre a participação no PVP, onde constatamos que, quanto a participação, os trabalhadores mostraram várias formas de uso do projeto, bem como tipos de participação, com ênfase às falas que esperam que o PVP também forme multiplicadores. Dentre os ganhos para a classe trabalhadora, no segundo tópico, eles citaram a melhoria da cultura de denúncia e a oportunidade de reconhecimento da identidade de gênero de uma classe em especial. Outros trabalhadores consideram o projeto, também, como agente fortalecedor de sua ou de outras categorias profissionais. No terceiro tópico, consideram que, no futuro, o PVP será uma importante ferramenta nas mãos do trabalhador para a exposição de sua realidade de trabalho. Além disso, eles colocam a esperança na melhoria do convívio com o próprio grupo do PVP no Rio de Janeiro. Por fim, no quarto tópico como melhorias, os entrevistados apontam a necessidade de reorganização do coletivo que compõe o PVP RJ. E para que esse convívio se concretize, os trabalhadores cobram que a Rede de Apoio realize mais reuniões. Outro ponto bem enfático na fala dos entrevistados, neste tópico, foi a dificuldade em acessar o site e a dificuldade de acesso à internet. Portanto, neste estudo observamos como a tecnologia da informação, associada a rede mundial de computadores e guiados pela experiência da metodologia da educação popular em saúde, se mostrou uma ferramenta de auxílio para a participação de trabalhadores em um projeto de saúde do trabalhador. No entanto, observamos que lidar com a metodologia a qual o projeto foi calcado trouxe dificuldades para a maturação dele no Rio de Janeiro. Também foi constatado a dificuldade de alguns trabalhadores em lidar com o componente digital do PVP. E, por fim, a reclamação implícita na fala dos trabalhadores em se sentir participante em todas as etapas da constituição do PVP.

Mudanças de Estado e Multiplicadores Fiscais no Brasil entre 1999-2012

Este trabalho avalia o comportamento dos multiplicadores fiscais no Brasil entre 1999-2012. Para tanto, utiliza a metodologia desenvolvida por Sims, Waggoner e Zha (2008), que é um procedimento Bayesiano de estimação no qual os parâmetros do modelo mudam com alterações no estado da economia e os estados (regimes) seguem um processo de mudança de regime markoviano. Ou seja, foi estimado um modelo VAR Estrutural Bayesiano com mudança de regimes Markoviana (Markov Switching Structural Bayesian Vector Autoregression - MS-SBVAR). A base de dados é composta pelo consumo da administração pública, pela formação bruta de capital fixo da administração pública, pela carga tributária líquida e pelo Produto Interno Bruto (PIB), das três esferas do governo (federal, estadual, incluindo o Distrito Federal, e municipal). O software MATLAB/Dynare foi utilizado na estimação dos modelos e os resultados sugerem a ocorrência de 2 ou 3 regimes nos dois modelos que melhor se ajustaram aos dados. Os multiplicadores estimados apresentaram os sinais esperados e os diferentes tipos de multiplicadores fiscais calculados apresentaram valores maiores para a resposta do PIB a choques na formação bruta de capital fixo da administração pública que são eficazes, uma vez que possuem valores maiores do que um e impacto de longo prazo no PIB - quando comparado aos choques no consumo da administração pública, que possuem pouca persistência e são ineficazes (menores do que um), além de uma resposta negativa e persistente do PIB a choques na carga tributária líquida. Os resultados obtidos não indicam, ainda, multiplicadores fiscais maiores em regimes com maior variância nos resíduos do modelo.

Change propagation analysis in complex technical systems

Understanding how and why changes propagate during engineering design is critical because most products and systems emerge from predecessors and not through clean sheet design. This paper applies change propagation analysis methods and extends prior reasoning through examination of a large data set from industry including 41,500 change requests, spanning 8 years during the design of a complex sensor system. Different methods are used to analyze the data and the results are compared to each other and evaluated in the context of previous findings. In particular the networks of connected parent, child and sibling changes are resolved over time and mapped to 46 subsystem areas. A normalized change propagation index (CPI) is then developed, showing the relative strength of each area on the absorber-multiplier spectrum between -1 and +1. Multipliers send out more changes than they receive and are good candidates for more focused change management. Another interesting finding is the quantitative confirmation of the "ripple" change pattern. Unlike the earlier prediction, however, it was found that the peak of cyclical change activity occurred late in the program driven by systems integration and functional testing. Patterns emerged from the data and offer clear implications for technical change management approaches in system design. Copyright © 2007 by ASME.

Packing LUT clusters with network flow programming

This paper describes a two-step packing algorithm for LUT clusters of which the LUT input multipliers are depopulated. In the first step, a greedy algorithm is used to search for BLE locations and cluster inputs. If the greedy algorithm fails, the second step with network flow programming algorithm is employed. Numerical results illustrate that our two-step packing algorithm obtains better packing density than one-step greedy packing algorithm.

Optimisation of Smart Grid performance using centralised and distributed control techniques

A massive change is currently taking place in the manner in which power networks are operated. Traditionally, power networks consisted of large power stations which were controlled from centralised locations. The trend in modern power networks is for generated power to be produced by a diverse array of energy sources which are spread over a large geographical area. As a result, controlling these systems from a centralised controller is impractical. Thus, future power networks will be controlled by a large number of intelligent distributed controllers which must work together to coordinate their actions. The term Smart Grid is the umbrella term used to denote this combination of power systems, artificial intelligence, and communications engineering. This thesis focuses on the application of optimal control techniques to Smart Grids with a focus in particular on iterative distributed MPC. A novel convergence and stability proof for iterative distributed MPC based on the Alternating Direction Method of Multipliers is derived. Distributed and centralised MPC, and an optimised PID controllers' performance are then compared when applied to a highly interconnected, nonlinear, MIMO testbed based on a part of the Nordic power grid. Finally, a novel tuning algorithm is proposed for iterative distributed MPC which simultaneously optimises both the closed loop performance and the communication overhead associated with the desired control.

Compilation and analysis of integrated regional input-output tables for NUTS 2 regions in Ireland

In 1966, Roy Geary, Director of the ESRI, noted “the absence of any kind of import and export statistics for regions is a grave lacuna” and further noted that if regional analyses were to be developed then regional Input-Output Tables must be put on the “regular statistical assembly line”. Forty-five years later, the lacuna lamented by Geary still exists and remains the most significant challenge to the construction of regional Input-Output Tables in Ireland. The continued paucity of sufficient regional data to compile effective regional Supply and Use and Input-Output Tables has retarded the capacity to construct sound regional economic models and provide a robust evidence base with which to formulate and assess regional policy. This study makes a first step towards addressing this gap by presenting the first set of fully integrated, symmetric, Supply and Use and domestic Input-Output Tables compiled for the NUTS 2 regions in Ireland: The Border, Midland and Western region and the Southern & Eastern region. These tables are general purpose in nature and are consistent fully with the official national Supply & Use and Input-Output Tables, and the regional accounts. The tables are constructed using a survey-based or bottom-up approach rather than employing modelling techniques, yielding more robust and credible tables. These tables are used to present a descriptive statistical analysis of the two administrative NUTS 2 regions in Ireland, drawing particular attention to the underlying structural differences of regional trade balances and composition of Gross Value Added in those regions. By deriving regional employment multipliers, Domestic Demand Employment matrices are constructed to quantify and illustrate the supply chain impact on employment. In the final part of the study, the predictive capability of the Input-Output framework is tested over two time periods. For both periods, the static Leontief production function assumptions are relaxed to allow for labour productivity. Comparative results from this experiment are presented.

Multiplier-less realization of a poly-phase filter using LUT-based FPGAs

In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.

Power Efficient Dynamic-Range Utilisation for DSP On FPGA

A power and resource efficient ‘dynamic-range utilisation’ technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data epresentation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.

Power Efficient DSP Datapath Configuration Methodology for FPGA

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

Neural network forecasts of input-output technology

A significant part of the literature on input-output (IO) analysis is dedicated to the development and application of methodologies forecasting and updating technology coefficients and multipliers. Prominent among such techniques is the RAS method, while more information demanding econometric methods, as well as other less promising ones, have been proposed. However, there has been little interest expressed in the use of more modern and often more innovative methods, such as neural networks in IO analysis in general. This study constructs, proposes and applies a Backpropagation Neural Network (BPN) with the purpose of forecasting IO technology coefficients and subsequently multipliers. The RAS method is also applied on the same set of UK IO tables, and the discussion of results of both methods is accompanied by a comparative analysis. The results show that the BPN offers a valid alternative way of IO technology forecasting and many forecasts were more accurate using this method. Overall, however, the RAS method outperformed the BPN but the difference is rather small to be systematic and there are further ways to improve the performance of the BPN.

FPGA montgomery modular multiplication architectures suitable for ECCs over GF(p)

New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18×18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in Elliptic Curve Cryptosystems over GF(p), which require modular field multiplication to perform elliptic curve point addition and doubling. Field sizes of 128-bits and 256-bits are chosen but other field sizes can easily be accommodated, by rapidly reprogramming the FPGA. Overall, the larger the word size of the multiplier, the more efficiently it performs in terms of area/time product. Also, the FIOS algorithm is flexible in that one can tailor the multiplier architecture is to be area efficient, time efficient or a mixture of both by choosing a particular word size. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 4.8 ms.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Ideals of A(G) and bimodules over maximal abelian selfadjoint algebras

This paper is concerned with weak⁎ closed masa-bimodules generated by A(G)-invariant subspaces of VN(G). An annihilator formula is established, which is used to characterise the weak⁎ closed subspaces of B(L2(G)) which are invariant under both Schur multipliers and a canonical action of M(G) on B(L2(G)) via completely bounded maps. We study the special cases of extremal ideals with a given null set and, for a large class of groups, we establish a link between relative spectral synthesis and relative operator synthesis.