A Novel, Balanced, and Energy-Efficient Training Method for Receive Antenna Selection

In receive antenna selection (AS), only signals from a subset of the antennas are processed at any time by the limited number of radio frequency (RF) chains available at the receiver. Hence, the transmitter needs to send pilots multiple times to enable the receiver to estimate the channel state of all the antennas and select the best subset. Conventionally, the sensitivity of coherent reception to channel estimation errors has been tackled by boosting the energy allocated to all pilots to ensure accurate channel estimates for all antennas. Energy for pilots received by unselected antennas is mostly wasted, especially since the selection process is robust to estimation errors. In this paper, we propose a novel training method uniquely tailored for AS that transmits one extra pilot symbol that generates accurate channel estimates for the antenna subset that actually receives data. Consequently, the transmitter can selectively boost the energy allocated to the extra pilot. We derive closed-form expressions for the proposed scheme's symbol error probability for MPSK and MQAM, and optimize the energy allocated to pilot and data symbols. Through an insightful asymptotic analysis, we show that the optimal solution achieves full diversity and is better than the conventional method.

Energy efficient asymmetric binary search switching technique for SAR ADC

An asymmetric binary search switching technique for a successive approximation register (SAR) ADC is presented, and trade-off between switching energy and conversion cycles is discussed. Without using any additional switches, the proposed technique consumes 46% less switching energy, for a small input swing (0.5 V-ref (P-P)), as compared to the last reported efficient switching technique in literature for an 8-bit SAR ADC. For a full input swing (2 V-ref (P-P)), the proposed technique consumes 16.5% less switching energy.

Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a non-fault-tolerant baseline and has a performance overhead of just 1.2%.

Energy-efficient redundant execution for chip multiprocessors

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

Energy-efficient synthesis of ferrite powders and films

In recent years, there has been significant effort in the synthesis of nanocrystalline spinel ferrites due to their unique properties. Among them, zinc ferrite has been widely investigated for countless applications. As traditional ferrite synthesis methods are energy- and time-intensive, there is need for a resource-effective process that can prepare ferrites quickly and efficiently without compromising material quality. We report on a novel microwave-assisted soft-chemical synthesis technique in the liquid medium for synthesis of ZnFe2O4 powder below 100 °C, within 5 min. The use of β-diketonate precursors, featuring direct metal-to-oxygen bonds in their molecular structure, not only reduces process temperature and duration sharply, but also leads to water-soluble and non-toxic by-products. As synthesized powder is annealed at 300 °C for 2 hrs in a conventional anneal (CA) schedule. An alternative procedure, a 2-min rapid anneal at 300 °C (RA) is shown to be sufficient to crystallize the ferrite particles, which show a saturation magnetization (MS) of 38 emu/g, compared with 39 emu/g for a 2-hr CA. This signifies that our process is efficient enough to reduce energy consumption by ∼85% just by altering the anneal scheme. Recognizing the criticality of anneal process to the energy budget, a more energy-efficient variation of the reaction process was developed, which obviates the need for post-synthesis annealing altogether. It is shown that the process also can be employed to deposit crystalline thin films of ferrites.

Energy-efficient training for antenna selection in time-varying channels

Training for receive antenna selection (AS) differs from that for conventional multiple antenna systems because of the limited hardware usage inherent in AS. We analyze and optimize the performance of a novel energy-efficient training method tailored for receive AS. In it, the transmitter sends not only pilots that enable the selection process, but also an extra pilot that leads to accurate channel estimates for the selected antenna that actually receives data. For time-varying channels, we propose a novel antenna selection rule and prove that it minimizes the symbol error probability (SEP). We also derive closed-form expressions for the SEP of MPSK, and show that the considered training method is significantly more energy-efficient than the conventional AS training method.

Energy Efficient GPS Acquisition with Sparse-GPS

Following rising demands in positioning with GPS, low-cost receivers are becoming widely available; but their energy demands are still too high. For energy efficient GPS sensing in delay-tolerant applications, the possibility of offloading a few milliseconds of raw signal samples and leveraging the greater processing power of the cloud for obtaining a position fix is being actively investigated. In an attempt to reduce the energy cost of this data offloading operation, we propose Sparse-GPS(1): a new computing framework for GPS acquisition via sparse approximation. Within the framework, GPS signals can be efficiently compressed by random ensembles. The sparse acquisition information, pertaining to the visible satellites that are embedded within these limited measurements, can subsequently be recovered by our proposed representation dictionary. By extensive empirical evaluations, we demonstrate the acquisition quality and energy gains of Sparse-GPS. We show that it is twice as energy efficient than offloading uncompressed data, and has 5-10 times lower energy costs than standalone GPS; with a median positioning accuracy of 40 m.

Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems

This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

Quick, Decentralized, Energy-Efficient One-Shot Max Function Computation Using Timer-Based Selection

In several wireless sensor networks, it is of interest to determine the maximum of the sensor readings and identify the sensor responsible for it. We propose a novel, decentralized, scalable, energy-efficient, timer-based, one-shot max function computation (TMC) algorithm. In it, the sensor nodes do not transmit their readings in a centrally pre-defined sequence. Instead, the nodes are grouped into clusters, and computation occurs over two contention stages. First, the nodes in each cluster contend with each other using the timer scheme to transmit their reading to their cluster-heads. Thereafter, the cluster-heads use the timer scheme to transmit the highest sensor reading in their cluster to the fusion node. One new challenge is that the use of the timer scheme leads to collisions, which can make the algorithm fail. We optimize the algorithm to minimize the average time required to determine the maximum subject to a constraint on the probability that it fails to find the maximum. TMC significantly lowers average function computation time, average number of transmissions, and average energy consumption compared to approaches proposed in the literature.

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

Which policy option can be more cost-effective in promoting the use of energy efficient appliances in Europe? A comparison of energy taxes, subsidies, tax credits and bans.

4 p.

The use of “Bonus-Malus” schemes for promoting energy-efficient household appliances: a case study for Spain

32 p.