High-performance evanescently-coupled uni-traveling-carrier photodiodes

A new evanescently-coupled uni-traveling-carrier photodiode (EC-UTC PD) based on a multimode diluted waveguide (MDW) structure is fabricated, analysed and characterized. Optical and electrical characteristics of the device are investigated. The excellent characteristics are demonstrated such as a responsivity of 0.36 A/W, a bandwidth of 11.5 GHz and a small-signal 1-dB compression current greater than 18 mA at 10 GHz. The saturation current is significantly improved compared with those of similar evanescently-coupled pin photodiodes. The radio frequency (RF) bandwidth can be further improved by eliminating RF losses induced by the cables, the probe and the bias tee between the photodiode and the spectrum analyzer.

Silica and alumina thin films grown by liquid phase deposition

This work demonstrates the condition optimization during liquid phase deposition (LPD) Of SiO2/GaAs films. LPD method is further applied to form Al2O3 films on semiconductors with poison-free materials. Proceeding at room temperature with inexpensive equipment, LPD of silica and alumina films is potentially serviceable in microelectronics and related spheres.

Effect of heavily doped boron on bandgap narrowing of strained SiGe layers

Taking into account the compensation effect of B to Ge in strained SiGe layers for the first time, the effect of heavily doped boron on the bandgap narrowing of strained SiGe layers is calculated, and the classical Jain-Roulston (J-R) model is modified. The results show that our modified J-R model well fits the experimental values. Based on the modified J-R model, the real bandgap narrowing distribution between the conduction and valence bands is further calculated, which has great influence on modelling the electrical characteristics of SiGe heterojunction bipolar transistors.

Photoluminescence and activation on SI-GaAs by Si+ implantation and following rapid thermal annealing

Photoluminescence (PL) and electrical characteristics of SI-GaAs, Si+-implanted and following rapid thermal annealing (RTA), were investigated, The PL spectra of Si-GA-C-As, Ga-i-Si-As, and V-As-Si-As were obtained. This paper concentrates on the PL peak at 1.36 eV which was proven as an emission of the Si-Ga-V-Ga combination by Si+ + P+ dual implantation. The results indicate that the peak at 1.36 eV appears when the ratio of As:Ga increased during the processing. Also high activation was obtained for the sample under the same conditions. More discussion on the mechanism of Si+ implanted SI-GaAs has been made based on the Morrow model [J. Appl. Phys, 64 (1988) 1889].

Homoepitaxial Growth of 4H-SiC and Ti/4H-SiC SBDs

Homoepitaxial growth of4H-SiC on off-oriented Si-face （0001） 4H-SiC substrates was performed at 1500℃ by using the step controlled Epitaxy. Ti/4H-SiC Schottky barrier diodes （SBDs） with blocking voltage over lkV have been made on an undoped epilayer with 32μm in thick and 2-5 × 10^15 cm^-3 in carrier density. The diode rectification ratio of forward to reverse （defined at ± 1V） is over 107 at room temperature and over 10^2 at 538K. Their electrical characteristics were studied by the current-voltage measurements in the temperature range from 20 to 265 ℃. The ideality factor and Schottky barrier height obtained at room temperature are 1.33 and 0. 905eV, respectively. The SBDs have on-state current density of 150A/cm^2 at a forward voltage drop of about 2.0V. The specific on-resistance for the rectifier is found to be as 7.9mΩ · cm^2 and its variation with temperature is T^2.0.

Tuning the emissive colour of top-emitting organic light-emitting diodes by using exterior multilayer films

We demonstrate an approach for realizing colour-controllable light emission from top-emitting organic light-emitting diodes (TEOLEDs) by utilizing exterior multilayer films overlaid on them. The emissive colour varies from blue to red for the TEOLED with green tris(8-quinolinolato) aluminium as the emissive layer by tuning the exterior multilayer films. The theoretical simulation of the electroluminescence for the colour tunable TEOLEDs is demonstrated and accords well with experimental results. The advantage of this approach is that the optical and electrical characteristics of the TEOLED can be controlled individually and hence provides the feasibility to realize a full-colour display by using white TEOLEDs.

Thickness dependence of mobility in CuPc thin film on amorphous SiO2 substrate

Hole mobility in a copper-phthalocyanine (CuPc)-based top-contact transistor has been studied with various organic layer thicknesses. It is found that the transistor performance depends on the thickness of the CuPc layer, and the mobility increases with the increase in the CuPc layer and saturated at the thickness of 6 ML. The upper layers do not actively contribute to the carrier transport in the organic films. The morphology of the organic layer grown on the bare SiO2/Si substrate is also presented. The analysis of spatial correlations shows that the CuPc films grow on the SiO2 according to the mixed-layer mode.

Heterojunction ambipolar organic transistors fabricated by a two-step vacuum-deposition process

Ambipolar organic field-effect transistors (OFETs) are produced, based on organic heterojunctions fabricated by a two-step vacuum-deposition process. Copper phthalocyanine (CuPc) deposited at a high temperature (250 degrees C) acts as the first (p-type component) layer, and hexadecafluorophthalocyaninatocopper (F16CuPc) deposited at room temperature (25 degrees C) acts as the second (n-type component) layer. A heterojunction with an interpenetrating network is obtained as the active layer for the OFETs. These heterojunction devices display significant ambipolar charge transport with symmetric electron and hole mobilities of the order of 10(-4) cm(2) V-1 s(-1) in air. Conductive channels are at the interface between the F16CuPc and CuPc domains in the interpenetrating networks. Electrons are transported in the F16CuPc regions, and holes in the CuPc regions. The molecular arrangement in the heterojunction is well ordered, resulting in a balance of the two carrier densities responsible for the ambipolar electrical characteristics. The thin-film morphology of the organic heterojunction with its interpenetrating network structure can be controlled well by the vacuum-deposition process.

The Role of Chemical Mechanisms in Neural Computation and Learning

Most computational models of neurons assume that their electrical characteristics are of paramount importance. However, all long-term changes in synaptic efficacy, as well as many short-term effects, are mediated by chemical mechanisms. This technical report explores the interaction between electrical and chemical mechanisms in neural learning and development. Two neural systems that exemplify this interaction are described and modelled. The first is the mechanisms underlying habituation, sensitization, and associative learning in the gill withdrawal reflex circuit in Aplysia, a marine snail. The second is the formation of retinotopic projections in the early visual pathway during embryonic development.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Computational modeling of defects in nanoscale device materials

This PhD thesis concerns the computational modeling of the electronic and atomic structure of point defects in technologically relevant materials. Identifying the atomistic origin of defects observed in the electrical characteristics of electronic devices has been a long-term goal of first-principles methods. First principles simulations are performed in this thesis, consisting of density functional theory (DFT) supplemented with many body perturbation theory (MBPT) methods, of native defects in bulk and slab models of In0.53Ga0.47As. The latter consist of (100) - oriented surfaces passivated with A12O3. Our results indicate that the experimentally extracted midgap interface state density (Dit) peaks are not the result of defects directly at the semiconductor/oxide interface, but originate from defects in a more bulk-like chemical environment. This conclusion is reached by considering the energy of charge transition levels for defects at the interface as a function of distance from the oxide. Our work provides insight into the types of defects responsible for the observed departure from ideal electrical behaviour in III-V metal-oxidesemiconductor (MOS) capacitors. In addition, the formation energetics and electron scattering properties of point defects in carbon nanotubes (CNTs) are studied using DFT in conjunction with Green’s function based techniques. The latter are applied to evaluate the low-temperature, low-bias Landauer conductance spectrum from which mesoscopic transport properties such as the elastic mean free path and localization length of technologically relevant CNT sizes can be estimated from computationally tractable CNT models. Our calculations show that at CNT diameters pertinent to interconnect applications, the 555777 divacancy defect results in increased scattering and hence higher electrical resistance for electron transport near the Fermi level.

Experimental and modeling analysis of the reliability of the anisotropic conductive films

Experiments as well as computer modeling methods have been used to investigate the effect of the solder reflow process on the electrical characteristics and reliability of anisotropic conductive film (ACF) interconnections. In the experiments, the contact resistance of the ACF interconnections was found to increase after a subsequent reflow and the magnitude of this increase was strongly correlated to the peak temperature of the reflow profile. In fact, nearly 40 percent of the joints were opened (i.e. lifted away from the pad) after the reflow with a peak temperature of 260 OC while no openings was observed when the peak temperature was 210 "C. It is believed that the CTE mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. To understand this phenomenon better, a 3-D model of an ACF joint structure was built and Finite Element Analysis was used to predict the stress distrihution in the conductive particles, adhesive matrix and metal pads during the reflow process. The effects of the peak temperature, the CTE of the adhesive matrix and the bump height on the reliability of the ACF interconnections were discussed.

Element suitability for circularly polarised phase agile reflectarray applications

The electrical characteristics of various elements that can be used as spatial phase shifters in circularly polarised (CP) reflectarrays are contrasted. The elements investigated are; a single rotating dipole at 10.3 GHz; a multiple dipole at 18.2 GHz; a rotating stub at 2.8 GHz; and a periphery point short-circuited circular patch at 3.0 GHz. For each element type, results are presented for the reflection phase, polarisation purity and reflection loss. Where appropriate, experiments are performed using the waveguide simulator technique to validate the numerical EM simulation.

A theoretical study of the effects of lithium intercalation on the electronic structure of TiS

The band structure of the intercalation complex of LiTiS has been computed using a semi-empirical tight-binding method and this is compared with the results of a revised TiS calculation. The results obtained confirm that changes in the basic electrical characteristics of TiS, which occur when it is intercalated with lithium, can be attributed to a rigid-band filling of its lowest unoccupied electron states as has previously been proposed. However, they also suggest that intercalation can act to alter the nature and the dispersion of some of the energy bands in the unintercalated crystal. The bands which are most affected by the process are those which derive from orbitals which have the same symmetry as the lithium 2s orbital, namely, the titanium 4s conduction level and the tightly bound sulphur 3s levels.