Underlap Optimization in HFinFET in Presence of Interface Traps

In this work, using 3-D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the ON-OFF ratio as well as the subthreshold characteristics in an ultrashort channel n-type device without significantON performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be promising when compared against ITRS 2009 performance projections, as well as published state of the art planar and nonplanar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

A power scalable receiver front-end at 2.4 GHz

We propose a Low Noise Amplifier (LNA) architecture for power scalable receiver front end (FE) for Zigbee. The motivation for power scalable receiver is to enable minimum power operation while meeting the run-time performance needed. We use simple models to find empirical relations between the available signal and interference levels to come up with required Noise Figure (NF) and 3rd order Intermodulation Product (IIP3) numbers. The architecture has two independent digital knobs to control the NF and IIP3. Acceptable input match while using adaptation has been achieved by using an Active Inductor configuration for the source degeneration inductor of the LNA. The low IF receiver front end (LNA with I and Q mixers) was fabricated in 130nm RFCMOS process and tested.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

A Novel VSI- and CSI-Fed Active-Reactive Induction Motor Drive with Sinusoidal Voltages and Currents

Till date load-commutated inverter (LCI)-fed synchronous motor drive configuration is popular in high power applications (>10 MW). The leading power factor operation of synchronous motor by excitation control offers this simple and rugged drive structure. On the contrary, LCI-fed induction motor drive is absent as it always draws lagging power factor current. Therefore, complicated commutation circuit is required to switch off thyristors for a current source inverter (CSI)-driven induction motor. It poses the major hindrance to scale up the power rating of CSI-fed induction motor drive. Anew power topology for LCI-fed induction motor drive for medium-voltage drive application is proposed. A new induction machine (active-reactive induction machine) with two sets of three-phase winding is introduced as a drive motor. The proposed power configuration ensures sinusoidal voltage and current at the motor terminals. The total drive power is shared among a thyristor-based LCI, an insulated gate bipolar transistor (IGBT)-based two-level voltage source inverter (VSI), and a three-level VSI. The benefits of SCRs and IGBTs are explored in the proposed drive. Experimental results from a prototype drive verify the basic concepts of the drive.

New approach to distance relays with quadrilateral polar characteristic for e.h.v.-line protection

A new technique is presented using principles of multisignal relaying for the synthesis of a universal-type quadrilateral polar characteristic. The modus operandi consists in the determination of the phase sequence of a set of voltage phasors and the provision of a trip signal for one sequence while blocking for the other. Two versions, one using ferrite-core logic and another using transistor logic, are described in detail. The former version has the merit of simplicity and has the added advantage of not requiring any d.c. supply. The unit is flexible, as it permits independent control of the characteristic along the resistance and reactance axis through suitable adjustments of replica impedance angles. The maximum operating time is about 20ms for all switching angles, and with faults within 95% of the protected section. The maximum transient overreach is about 8%.

New static 3-step distance relay

A new static 3-step distance relay based on the principle of multi-input phase comparison is described in the paper. Design principles and typical discriminating and logic circuits are described for the new relaying system. The relaying system uses semiconductor circuits throughout and features high speed and good performance. The comparator model, which effects multi-input phase comparison, has been devised to provide reliable pickup for closein faults, and to achieve an improved polar characteristic in the complex- impedance plane, which fits around only the fault area of a transmission line. Operating time of the relay is less than 1 cycle for unbalanced faults, and less than a halfcycle for 3-phase faults. Protective circuits have also been added to detect power swing and to block tripping for a predetermined number of power-swing cycles. The operating characteristics of the relay, as expressed by accuracy/range charts, are presented.

Study of symmetrical and related components through the theory of linear vector spaces

The paper proposes a study of symmetrical and related components, based on the theory of linear vector spaces. Using the concept of equivalence, the transformation matrixes of Clarke, Kimbark, Concordia, Boyajian and Koga are shown to be column equivalent to Fortescue's symmetrical-component transformation matrix. With a constraint on power, criteria are presented for the choice of bases for voltage and current vector spaces. In particular, it is shown that, for power invariance, either the same orthonormal (self-reciprocal) basis must be chosen for both voltage and current vector spaces, or the basis of one must be chosen to be reciprocal to that of the other. The original �¿, ��, 0 components of Clarke are modified to achieve power invariance. For machine analysis, it is shown that invariant transformations lead to reciprocal mutual inductances between the equivalent circuits. The relative merits of the various components are discussed.

Three-system and single-system static distance relays

Static distance relays employing semiconductor devices as their active elements offer many advantages over the conventional electromagnetic and rectifier relays. The paper describes single-system and three-system static distance relays, which depend for their operation on the instantaneous-comparison or `block-spike¿ scheme. Design principles and typical discriminating and logic circuits are described for the new relaying equipment. The relaying circuitry has been devised for obtaining uniform performance on all kinds of faults, by the use of two phase detectors¿one for multiphase faults and one for earth faults. The phase detector for multiphase faults provides an improved polar characteristic in the complex-impedance plane, which fits only around the fault area of a transmission line. The other features of the relay are: reliable pickup for close-in faults, least susceptibility to maloperation under power-swing conditions, and reduction in cost and panel space required. The operating characteristics of the relays, as expressed by accuracy/range charts, are also presented.

Bypass operation in bridge convertors for high-voltage d.c. transmission

Bypass operation with the aid of a special bypass valve is an important part of present-day schemes of protection for h.v. d.c. transmission systems. In this paper, the possibility of using two valves connected to any phase in the bridge convertor for the purpose of bypass operation is studied. The scheme is based on the use of logic circuits in conjunction with modified methods of fault detection. Analysis of the faults in a d.c. transmission system is carried out with the object of determining the requirements of such a logic-circuit control system. An outline of the scheme for the logic-circuit control of the bypass operation for both rectifier and invertor bridges is then given. Finally, conclusions are drawn regarding the advantages of such a system, which include reduction in the number of valves, prevention of severe faults and fast clearance of faults, in addition to the immediate location of the fault and its nature.

Developments in solid-state under-frequency relays

Simpler circuits for frequency-sensitive relays responding to change and rate of change of system frequency have been developed employing phase-locked loops. A new relay responding to time intergral of the fall in system frequency has also been developed and its performance has been compared with those responding to change and rate of change of system frequency. The relays have been tested and calibrated with the help of a specially designed calibration kit.

Characteristics of j.f.e.t.s. taking the separation of gate electrode from the source and drain electrodes into account

The performance characteristics of a junction field-effect transistor (j.f.e.t.) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals. It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current. So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier. The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel. For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain.

Influence of Phase Connection and Terminal Conditions on Natural Frequencies of Three-Phase Transformer Windings

With the increasing use of extra high-voltage transmission in power system expansion, the manufacturers of power apparatus and the electric utilities are studying the nature of overvoltages in power systems due to lightning and, in particular, switching operations. For such analyses, knowledge of the natural frequencies of the windings of transformers under a wide variety of conditions is important. The work reported by the author in a previous paper is extended and equivalent circuits have been developed to represent several sets of terminal conditions. These equivalent circuits can be used to determine the natural frequencies and transient voltages in the windings. Comparison of the measured and the computed results obtained with a model transformer indicates that they are in good agreement. Hence, this method of analysis provides a satisfactory procedure for the estimation of natural frequencies and transient voltages in transformer windings.