High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit

In this paper we propose a fully parallel 64K point radix-4(4) FFT processor. The radix-4(4) parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. The radix-4(4) block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. The resultant 64K point FFT processor shows significant reduction in intermediate memory but with increased hardware complexity. Compared to the state-of-art implementation 5], our architecture shows reduced latency with comparable throughput and area. The 64K point FFT architecture was synthesized using a 130nm CMOS technology which resulted in a throughput of 1.4 GSPS and latency of 47.7 mu s with a maximum clock frequency of 350MHz. When compared to 5], the latency is reduced by 303 mu s with 50.8% reduction in area.

External support and innovation performance of SMEs in Bangalore: Role of firm level factors

This paper probes the role of internal factors in SMEs in obtaining external support and achieving innovation performance in the context of auto component, electronics and machine tool industries of Bangalore in India. Using step-wise logistic regression analysis, the study found that only if SMEs have internal technical competence in terms of technically qualified entrepreneur, an exclusive design centre, and innovate more frequently, they will be able to obtain external support. Further using step-wise multiple regression the study concluded that SMEs which have come up to implement innovative ideas or exploit market opportunities and which have obtained external support with technically qualified entrepreneurs are able to exhibit better innovation performance.

Germanane: a Low Effective Mass and High Bandgap 2-D Channel Material for Future FETs

We investigate the electronic properties of Germanane and analyze its importance as 2-D channel material in switching devices. Considering two types of morphologies, namely, chair and boat, we study the real band structure, the effective mass variation, and the complex band structure of unstrained Germanane by density-functional theory. The chair morphology turns out to be a more effective channel material for switching devices than the boat morphology. Furthermore, we study the effect of elastic strain, van der Waals force, and vertical electric field on these band structure properties. Due to its very low effective mass with relatively high-energy bandgap, in comparison with the other 2-D materials, Germanane appears to provide superior performance in switching device applications.

How Does Effectual Logic Impact Survival of High-tech Startups in an Emerging Economy? - Evidence from 99tests.com Case Study

During the early stages of operation, high-tech startups need to overcome the liability of newness and manage high degree of uncertainty. Several high-tech startups fail due to inability to deal with skeptical customers, underdeveloped markets and limited resources in selling an offering that has no precedent. This paper leverages the principles of effectuation (a logic of entrepreneurial decision making under uncertainty) to explain the journey from creation to survival of high-tech startups in an emerging economy. Based on the 99tests.com case study, this paper suggests that early stage high-tech startups in emerging economies can increase their probability of survival by adopting the principles of effectuation.

Effect of processing route on phase stability in equiatomic multicomponent Ti20Fe20Ni20Co20Cu20 high entropy alloy

The evolution of microstructure and phase formation in equiatomic Ti20Fe20Ni20Co20Cu20 high entropy alloy synthesised by conventional arc melting followed with suction casting and ball milling with spark plasma sintering route is distinctly different. The cast microstructure exhibits one body centre cubic and two face centre cubic high entropy phases based on titanium, cobalt and copper respectively along with a eutectic containing Ti2Ni type Laves phase. On the contrary, spinodal decomposed microstructure consisting of cobalt and copper solid solution is obtained in the sintered sample. However, long term annealing of cast sample at 950 degrees C reveals a eutectoid transformation with different phases than the cast sample. The aforementioned observations are discussed using CALPHAD thermodynamical approach and available literature.

Innovation and growth of engineering SMEs in Bangalore: Why do only some innovate and only some grow faster?

This paper probes two research questions by ascertaining the factors which distinguish (i) innovative SMEs from those which are not, and (ii) SMEs which experienced a higher sales growth from those which experienced a lower sales growth, with reference to 197 engineering industry SMEs in Bangalore city. The differentiating factors between innovative and non-innovative SMEs brought out that SMEs must have ``own resources and capabilities'' in the form of internal strength and definite internal strategy if they have to innovate successfully. Younger and smaller firms which are ``entrepreneurial'' in nature and which are innovative contributed to higher sales growth of SMEs compared to older and larger firms which are ``salary-substitute firms'' in nature and which are not innovative. (C) 2015 Elsevier B.V. All rights reserved.

Continuous synthesis of high quality CdSe quantum dots in supercritical fluids

We demonstrate in here a powerful scalable technology to synthesize continuously high quality CdSe quantum dots (QDs) in supercritical hexane. Using a low cost, highly thermally stable Cd-precursor, cadmium deoxycholate, the continuous synthesis is performed in 400 mu m ID stainless steel capillaries resulting in CdSe QDs having sharp full-width-at-half-maxima (23 nm) and high photoluminescence quantum yields (45-55%). Transmission electron microscopy images show narrow particles sizes distribution (sigma <= 5%) with well-defined crystal lattices. Using two different synthesis temperatures (250 degrees C and 310 degrees C), it was possible to obtain zinc blende and wurtzite crystal structures of CdSe QDs, respectively. This synthetic approach allows achieving substantial production rates up to 200 mg of QDs per hour depending on the targeted size, and could be easily scaled to gram per hour.

High-Performance Stacked TiO2-ZrO2 and Si-doped ZrO2 Metal-Insulator-Metal Capacitors

Metal-insulator-metal (MIM) capacitors for DRAM applications have been realised using stacked TiO2-ZrO2 (TiO2/ZrO2 and ZrO2/TiO2) and Si-doped ZrO2 (TiO2/Si-doped ZrO2) dielectrics. High capacitance densities (> 42 fF/mu m(2)), low leakage current densities (< 5 x 10(-7) A/cm(2) at -1 V), and sub-nm EOT (< 0.8 nm) have been achieved. The effects of constant voltage stress on the device characteristics is studied. The structural analysis of the samples is performed by X-ray diffraction measurements, and this is correlated to the electrical characteristics of the devices. The surface chemical states of the films are analyzed through X-ray photoelectron spectroscopy measurements. The doped-dielectric stack (TiO2/Si-doped ZrO2) helps to reduce leakage current density and improve reliability, with a marginal reduction in capacitance density; compared to their undoped counterparts (TiO2/ZrO2 and ZrO2/TiO2). We compare the device performance of the fabricated capacitors with other stacked high-k MIM capacitors reported in recent literature.

Deformability Measurement of Single-Cells at High-Throughput With Imaging Flow Cytometry

Disease conditions like malaria, sickle cell anemia, diabetes mellitus, cancer, etc., are known to significantly alter the deformability of certain types of cells (red blood cells, white blood cells, circulating tumor cells, etc.). To determine the cellular deformability, techniques like micropipette aspiration, atomic force microscopy, optical tweezers, quantitative phase imaging have been developed. Many of these techniques have an advantage of determining the single cell deformability with ultrahigh precision. However, the suitability of these techniques for the realization of a deformability based diagnostic tool is questionable as they are expensive and extremely slow to operate on a huge population of cells. In this paper, we propose a technique for high-throughput (800 cells/s) determination of cellular deformability on a single cell basis. This technique involves capturing the image(s) of cells in flow that have undergone deformation under the influence of shear gradient generated by the fluid flowing through the microfluidic channels. Deformability indices of these cells can be computed by performing morphological operations on these images. We demonstrate the applicability of this technique for examining the deformability index on healthy, diabetic, and sphered red blood cells. We believe that this technique has a strong role to play in the realization of a potential tool that uses deformability as one of the important criteria in disease diagnosis.

Thermal test method for high power three-phase grid-connected inverters

Semiconductor device junction temperatures are maintained within datasheet specified limits to avoid failure in power converters. Burn-in tests are used to ensure this. In inverters, thermal time constants can be large and burn-in tests are required to be performed over long durations of time. At higher power levels, besides increased production cost, the testing requires sources and loads that can handle high power. In this study, a novel method to test a high power three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources and loads. Only energy corresponding to the losses is consumed. The test is done by circulating rated current within the three legs of the inverter. All the phase legs being loaded, the method can be used to test the inverter in both cases of a common or independent cooling arrangement for the inverter phase legs. Further, the method can be used with different inverter configurations - three- or four-wire and for different pulse width modulation (PWM) techniques. The method has been experimentally validated on a 24 kVA inverter for a four-wire configuration that uses sine-triangle PWM and a three-wire configuration that uses conventional space vector PWM.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

High performance sol-gel spin-coated titanium dioxide dielectric based MOS structures

High-kappa TiO2 thin films have been fabricated using cost effective sol-gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO2 films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 degrees C, retaining its structural integrity up to 1000 degrees C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance-voltage (C-V) characteristics of the films annealed at 400 degrees C exhibited a high value of dielectric constant (similar to 34). Further, frequency dependent C-V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO2/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent `s'=0.85). A low leakage current density of 3.6 x 10(-7) A/cm(2) at 1 V was observed for the films annealed at 600 degrees C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-kappa materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and AID. The results also suggest that the high value of dielectric constant kappa obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology. (C) 2015 Elsevier Ltd. All rights reserved.

High resolution cortical bone thickness measurement from clinical CT data.

The distribution of cortical bone in the proximal femur is believed to be a critical component in determining fracture resistance. Current CT technology is limited in its ability to measure cortical thickness, especially in the sub-millimetre range which lies within the point spread function of today's clinical scanners. In this paper, we present a novel technique that is capable of producing unbiased thickness estimates down to 0.3mm. The technique relies on a mathematical model of the anatomy and the imaging system, which is fitted to the data at a large number of sites around the proximal femur, producing around 17,000 independent thickness estimates per specimen. In a series of experiments on 16 cadaveric femurs, estimation errors were measured as -0.01+/-0.58mm (mean+/-1std.dev.) for cortical thicknesses in the range 0.3-4mm. This compares with 0.25+/-0.69mm for simple thresholding and 0.90+/-0.92mm for a variant of the 50% relative threshold method. In the clinically relevant sub-millimetre range, thresholding increasingly fails to detect the cortex at all, whereas the new technique continues to perform well. The many cortical thickness estimates can be displayed as a colour map painted onto the femoral surface. Computation of the surfaces and colour maps is largely automatic, requiring around 15min on a modest laptop computer.

High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al-1%Si membranes and has a low thermal budget (<450 °C) being compatible with CMOS post-processing. The proposed silicon sacrificial layer dry etching (SSLDE) process is able to provide very high Si etch rates (3-15 μm/min, depending on process parameters) with high Si: SiO2 selectivity (>10,000:1). Single- and double-air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S-parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications. © 2004 Elsevier B.V. All rights reserved.

High quality assembly of phase-only liquid crystal on silicon ((LCOS) devices

Liquid crystal on silicon (LCOS) for phase-only holography is ideally made to better optical tolerance than that for conventional amplitude modulating applications. Die-level assembly is suited to custom devices and pre-production prototypes because of its flexibility and efficiency in conserving the silicon backplane. Combined with automated assembly, it will allow high reproducibility and fast turnaround time, paving the way for pre-production testing and customer sampling before mass production. Pre-assembly optical testing is the key element in the process. By taking into account the flatness of both the backplane and the front glass plate, we have assembled high quality LCOS devices. We have reached our aim of less than one quarter wavelength phase distortion across the active area. © 2011 IEEE.