On The Energy-Efficiency of Byte-Addressable Non-Volatile Memory

Non-Volatile Memory (NVM) technology holds promise to replace SRAM and DRAM at various levels of the memory hierarchy. The interest in NVM is motivated by the difficulty faced in scaling DRAM beyond 22 nm and, long-term, lower cost per bit. While offering higher density and negligible static power (leakage and refresh), NVM suffers increased latency and energy per memory access. This paper develops energy and performance models of memory systems and applies them to understand the energy-efficiency of replacing or complementing DRAM with NVM. Our analysis focusses on the application of NVM in main memory. We demonstrate that NVM such as STT-RAM and RRAM is energy-efficient for memory sizes commonly employed in servers and high-end workstations, but PCM is not. Furthermore, the model is well suited to quickly evaluate the impact of changes to the model parameters, which may be achieved through optimization of the memory architecture, and to determine the key parameters that impact system-level energy and performance.

The effects of TMS over dorsolateral prefrontal cortex on trans-saccadic memory of multiple objects

Humans typically make several rapid eye movements (saccades) per second. It is thought that visual working memory can retain and spatially integrate three to four objects or features across each saccade but little is known about this neural mechanism. Previously we showed that transcranial magnetic stimulation (TMS) to the posterior parietal cortex and frontal eye fields degrade trans-saccadic memory of multiple object features (Prime, Vesia, & Crawford, 2008, Journal of Neuroscience, 28(27), 6938-6949; Prime, Vesia, & Crawford, 2010, Cerebral Cortex, 20(4), 759-772.). Here, we used a similar protocol to investigate whether dorsolateral prefrontal cortex (DLPFC), an area involved in spatial working memory, is also involved in trans-saccadic memory. Subjects were required to report changes in stimulus orientation with (saccade task) or without (fixation task) an eye movement in the intervening memory interval. We applied single-pulse TMS to left and right DLPFC during the memory delay, timed at three intervals to arrive approximately 100ms before, 100ms after, or at saccade onset. In the fixation task, left DLPFC TMS produced inconsistent results, whereas right DLPFC TMS disrupted performance at all three intervals (significantly for presaccadic TMS). In contrast, in the saccade task, TMS consistently facilitated performance (significantly for left DLPFC/perisaccadic TMS and right DLPFC/postsaccadic TMS) suggesting a dis-inhibition of trans-saccadic processing. These results are consistent with a neural circuit of trans-saccadic memory that overlaps and interacts with, but is partially separate from the circuit for visual working memory during sustained fixation.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Prediction of Limit Cycle Oscillations Using an Implicit Aeroelastic-Harmonic Balance Method

This work proposes a extends a novel approach to compute tran sonic Limit Cycle Oscillations using high fidelity analysis. CFD based Harmonic Balance methods have proven to be efficient tools to predict periodic phenomena. This paper’s contribution is to present a methodology to determine the unknown frequency of oscillations using an implicit for- mulation of the HB method to accurately capture Limit Cycle Oscillations (LCOs); this is achieved by defining a frequency updating procedure based on a coupled CFD/CSD Harmonic Balance formulation to find the LCO condition. A pitch/plunge aerofoil and respective linear structural models is used to exercise the new method. Results show consistent agreement between the proposed and time-marching methods for both LCO amplitude and frequency.

Distributed Region-Based Memory Allocation and Synchronization

We present DRASync, a region-based allocator that implements a global address space abstraction for MPI programs with pointer-based data structures. The main features of DRASync are: (a) it amortizes communication among nodes to allow efficient parallel allocation in a global address space; (b) it takes advantage of bulk deallocation and good locality with pointer-based data structures; (c) it supports ownership semantics of regions by nodes akin to reader–writer locks, which makes for a high-level, intuitive synchronization tool in MPI programs, without sacrificing message-passing performance. We evaluate DRASync against a state-of-the-art distributed allocator and find that it produces comparable performance while offering a higher-level abstraction to programmers.

A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

Competition between memory-keeping and memory-erasing decoherence channels

We study the competing effects of simultaneous Markovian and non-Markovian decoherence mechanisms acting on a single spin. We show the existence of a threshold in the relative strength of such mechanisms above which the spin dynamics becomes fully Markovian, as revealed by the use of several non-Markovianity measures. We identify a measure-dependent nested structure of such thresholds, hinting at a causality relationship among the various non-Markovianity witnesses used in our analysis. Our considerations are then used to argue the unavoidably non-Markovian evolution of a single-electron quantum dot exposed to both intrinsic and Markovian technical noise, the latter of arbitrary strength. 

Cyclic nanoindentation and nano-impact fatigue characterisation of functionally graded TiN/TiNi shape memory film

This paper investigates the mechanism of nanoscale fatigue of functionally graded TiN/TiNi films using nano-impact and multiple-loading-cycle nanoindentation tests. The functionally graded films were deposited on silicon substrate, in which TiNi films maintain shape memory and pseudo elastic behavior, while a modified TiN surface layer provides tribological and anti-corrosion properties. Nanomechanical tests were performed to comprehend the localized film performance and failure modes of the functionally graded film using NanoTestTM equipped with Berkovich and conical indenter between 100 μN to 500 mN loads. The loading mechanism and load history are critical to define film failure modes (i.e. backward depth deviation) including the shape memory effect of the functionally graded layer. The results are sensitive to the applied load, loading type (e.g. semi-static, dynamic) and probe geometry. Based on indentation force-depth profiles, depth-time data and post-test surface observations of films, it is concluded that the shape of the nanoindenter is critical in inducing the localized indentation stress and film failure, including shape recovery at the lower load range. Elastic-plastic finite element (FE) simulation during nanoindentation loading indicated that the location of subsurface maximum stress near the interface influences the backward depth deviation type of film failure. A standalone, molecular dynamics simulation was performed with the help of a long range potential energy function to simulate the tensile test of TiN nanowire with two different aspect ratios to investigate the theory of its failure mechanism.

Post-Conflict Performance, Film and Visual Arts:Cities of Memory

This book examines how contemporary theatre, performance, film and the visual arts respond to the post-conflict condition. The contents of the volume focus on a range of post-conflict cities, encouraging interdisciplinary discussion on the role of the arts and its relation to issues of testimony, witnessing, forgetting, representation, healing, reconciliation, agency, and metaphor. Contributors include: Thomas Elsaesser, Jane Taylor, Marvin Carlson, Rob Stone, Laurel Borisenko, Katarzyna Puzon, Miriam Paeslack, Emma Grey, Paula Blair, Zoran Poposki, Marija Todorova, Elena Carduro, and Paul Devlin.

Software-Managed Energy-Efficient Hybrid DRAM/NVM Main Memory

This paper evaluates the viability of user-level software management of a hybrid DRAM/NVM main memory system. We propose an operating system (OS) and programming interface to place data from within the user application. We present a profiling tool to help programmers decide on the placement of application data in hybrid memory systems. Cycle-accurate simulation of modified applications confirms that our approach is more energy-efficient than state-of-the- art hardware or OS approaches at equivalent performance. Moreover, our results are validated on several candidate NVM technologies and a wide set of 14 benchmarks.
The key observation behind this work is that, for the work- loads we evaluated, application objects are too short-lived to motivate migration. Utilizing this property significantly reduces the hardware complexity of hybrid memory systems.