A Hardware Acceleration Scheme for Memory-Efficient Flow Processing
| Data(s) |
02/09/2014
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| Resumo |
This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet. |
| Formato |
application/pdf |
| Identificador | |
| Idioma(s) |
eng |
| Publicador |
Institute of Electrical and Electronics Engineers (IEEE) |
| Direitos |
info:eu-repo/semantics/openAccess |
| Fonte |
Yang , X , Sezer , S & O'Neill , S 2014 , A Hardware Acceleration Scheme for Memory-Efficient Flow Processing . in 2014 27th IEEE International System-on-Chip Conference (SOCC) . Institute of Electrical and Electronics Engineers (IEEE) , pp. 437-442 , IEEE System-on-Chip Conference (SOCC) , Las Vegas , United States , 2-5 September . DOI: 10.1109/SOCC.2014.6948969 |
| Tipo |
contributionToPeriodical |
