A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

A Wide-Band Low Noise Amplifier for Terrestrial and Cable Receptions

We present the design of a wide-band low-noise amplifier （LNA） implemented in 0.35μm SiGe BiCMOS technology for cable and terrestrial tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1 ～ 1GHz wide bandwidth and 18. 8dB gain with less than 1.4dB of gain variation. The noise figure of the wideband LNA is 5dB, and its 1dB compression point is - 2dBm and IIP3 is 8dBm. The LNA dissipates 120mW of power with a 5V supply.

Carrier Depth Profile of Si/SiGe/Si n-p-n HBTStructural Materials Characterized by Electrochemical Capacitance- Voltage Method

于2010-11-23批量导入

Low-frequency noise properties of GaN Schottky barriers deposited on intermediate temperature buffer layers

Metal-semiconductor-metal (MSM) structures were fabricated by RF-plasma-assisted MBE using different buffer layer structures. One type of buffer structure consists of an AlN high-temperature buffer layer (HTBL) and a GaN intermediate temperature buffer layer (ITBL), another buffer structure consists of just a single A IN HTBL. Systematic measurements in the flicker noise and deep level transient Fourier spectroscopy (DLTFS) measurements were used to characterize the defect properties in the films. Both the noise and DLTFS measurements indicate improved properties for devices fabricated with the use of ITBL and is attributed to the relaxation of residue strain in the epitaxial layer during growth process. (C) 2003 Elsevier Ltd. All rights reserved.