Partitioning Heritability of Regulatory and Cell-Type-Specific Variants across 11 Common Diseases

Regulatory and coding variants are known to be enriched with associations identified by genome-wide association studies (GWASs) of complex disease, but their contributions to trait heritability are currently unknown. We applied variance-component methods to imputed genotype data for 11 common diseases to partition the heritability explained by genotyped SNPs () across functional categories (while accounting for shared variance due to linkage disequilibrium). Extensive simulations showed that in contrast to current estimates from GWAS summary statistics, the variance-component approach partitions heritability accurately under a wide range of complex-disease architectures. Across the 11 diseases DNaseI hypersensitivity sites (DHSs) from 217 cell types spanned 16% of imputed SNPs (and 24% of genotyped SNPs) but explained an average of 79% (SE = 8%) of  from imputed SNPs (5.1× enrichment; p = 3.7 × 10⁻¹⁷) and 38% (SE = 4%) of  from genotyped SNPs (1.6× enrichment, p = 1.0 × 10⁻⁴). Further enrichment was observed at enhancer DHSs and cell-type-specific DHSs. In contrast, coding variants, which span 1% of the genome, explained <10% of  despite having the highest enrichment. We replicated these findings but found no significant contribution from rare coding variants in independent schizophrenia cohorts genotyped on GWAS and exome chips. Our results highlight the value of analyzing components of heritability to unravel the functional architecture of common disease.

Non-covalent hydrogels of cyclodextrins and poloxamines for the controlled release of proteins

Different types of gels were prepared by combining poloxamines (Tetronic), i.e. poly(ethylene oxide)/poly(propylene oxide) (PEO/PPO) octablock star copolymers, and cyclodextrins (CD). Two different poloxamines with the same molecular weight (ca. 7000) but different molecular architectures were used. For each of their four diblock arms, direct Tetronic 904 presents PEO outer blocks while in reverse Tetronic 90R4 the hydrophilic PEO blocks are the inner ones. These gels were prepared by combining alpha-CD and poloxamine aqueous solutions. The physicochemical properties of these systems depend on several factors such as the structure of the block copolymers and the Tetronic/alpha-CD ratio. These gels were characterized using differential scanning calorimetry (DSC), viscometry and X-ray diffraction measurements. The 90R4 gels present a consistency that makes them suitable for sustained drug delivery. The resulting gels were easily eroded: these complexes were dismantled when placed in a large amount of water, so controlled release of entrapped large molecules such as proteins (Bovine Serum Albumin, BSA) is feasible and can be tuned by varying the copolymer/CD ratio. 

Polarization Distortion as a Means for Securing Wireless Communication

This paper presents a simple polarization encoding strategy that operates using only single element dual port transmit and receive antennas in such a way that selective spatial scrambling of QPSK data can be effected. The key transmitter and receiver relationships needed for this operation to occur are derived. The system is validated using a cross dipole antenna arrangement. Unlike all previously reported physical layer wireless solutions the approach developed in this paper transfers the security property to the receive side resulting in very simple transmit and receive side architectures thus avoiding the need for near field modulated array technology. In addition the scheme permits, for the first time, multiple spatially separated secured receive sites to operate in parallel.

Modulation Insensitive PLL for Tracking Antenna Applications

This article shows practical results of a self-tracking receiving antenna array using a new phase locked loop (PLL) tracking configuration. The PLL configuration differs from other architectures, as it has the new feature of being able to directly track phase modulated signals without requiring an additional unmodulated pilot carrier to be present. The PLLs are used within the antenna array to produce a constant phase intermediate frequency (IF) for each antenna element. These IF's can then be combined in phase, regardless of the angle of arrival of the signal, thus utilizing the antennas array factor. The article's main focus is on the phase jitter performance of the modulation insensitive PLL carrier recovery when tracking phase modulated signals of low signal to noise ratio. From this analysis, it is concluded that the new architecture, when optimally designed, can produce phase jitter performance close to that of a conventional tracking PLL.

Session organiser/chair: Architecture, Infrastructure and the Making of Modern Ireland

‘A free Ireland would drain the bogs, would harness the rivers, would plant the wastes, would nationalise the railways and the waterways, would improve agriculture, would protect fisheries, would foster industries, would promote commerce, and beautify the cities …’ (Padraig Pearse, ‘From a Hermitage’, 1913)

Somewhat unusually in his often romantic writings Padraig Pearse – poet, pedagogue and revolutionary – chose to describe the future of an independent Ireland in terms of infrastructure and technological processes. Terence Brown’s locating of this excerpt at the beginning his seminal work Ireland: A Social and Cultural History 1922-2002 highlights the simultaneous and interlinking construction of both a new physical and cultural landscape for an independent modern nation. Lacking any significant industrial complex, the construction of new infrastructures in Ireland was seen throughout the 20th century as a key element in the building of the new State, just as the adoption of an international style modernism in architecture was perceived as a way to escape the colonial past. For Paul N. Edwards modernity and infrastructure are intimately connected.

‘infrastructures simultaneously shape and are shaped – in other words, co-construct – the condition of modernity. By linking macro, meso, and micro scales of time, space and social organisation, they form the stable foundation of modern social worlds’ (2003: 186).
Simultaneously omnipresent and invisible – infra means beneath – Edwards also points out that infrastructure tends only to become apparent when it is either new or broken. Interpreting the meso scale as being that of the building, this session calls for papers that critically and analytically investigate aspects of the architectures of infrastructure in 20th-century Ireland. Like the territory they explore these papers may range across scales to oscillate between a concern for the artefact and its physical landscape, and the larger, often hidden systems and networks that co-define this architecture.

Accelerating integer-based fully homomorphic encryption using Comba multiplication

Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.

Pool Evolution: A Parallel Pattern for Evolutionary and Symbolic Computing

We introduce a new parallel pattern derived from a specific application domain and show how it turns out to have application beyond its domain of origin. The pool evolution pattern models the parallel evolution of a population subject to mutations and evolving in such a way that a given fitness function is optimized. The pattern has been demonstrated to be suitable for capturing and modeling the parallel patterns underpinning various evolutionary algorithms, as well as other parallel patterns typical of symbolic computation. In this paper we introduce the pattern, we discuss its implementation on modern multi/many core architectures and finally present experimental results obtained with FastFlow and Erlang implementations to assess its feasibility and scalability.

Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

Experiment of Digital Directional Modulation Transmitters

A digital directional modulation (DM) transmitter structure is proposed from a practical implementation point of view in this paper. This digital DM architecture is built with the help of several off-the-shelf physical layer wireless experiment platform hardware boards. When compared with previous analogue DM transmitter architectures, the digital means offers more precise and fast control on the updates of the array excitations. More importantly, it is an ideal physical arrangement to implement the most universal DM synthesis algorithm, i.e., the orthogonal vector approach. The practical issues in digital DM system calibrations are described and solved. The bit error rates (BERs) are measured via real-time data transmissions to illustrate the DM advantages, in terms of secrecy performance, over conventional non-DM beam-steering transmitters.

Very high speed 17 Gbps SHACAL encryption architecture

Very high speed and low area hardware architectures of the SHACAL-1 encryption algorithm are presented in this paper. The SHACAL algorithm was a submission to the New European Schemes for Signatures, Integrity and Encryption (NESSIE) project and it is based on the SHA-1 hash algorithm. To date, there have been no performance metrics published on hardware implementations of this algorithm. A fully pipelined SHACAL-1 encryption architecture is described in this paper and when implemented on a Virtex-II X2V4000 FPGA device, it runs at a throughput of 17 Gbps. A fully pipelined decryption architecture achieves a speed of 13 Gbps when implemented on the same device. In addition, iterative architectures of the algorithm are presented. The SHACAL-1 decryption algorithm is derived and also presented in this paper, since it was not provided in the submission to NESSIE. © Springer-Verlag Berlin Heidelberg 2003.

Mobile Wearable Communications

This special issue provides the latest research and development on wireless mobile wearable communications. According to a report by Juniper Research, the market value of connected wearable devices is expected to reach $1.5 billion by 2014, and the shipment of wearable devices may reach 70 million by 2017. Good examples of wearable devices are the prominent Google Glass and Microsoft HoloLens. As wearable technology is rapidly penetrating our daily life, mobile wearable communication is becoming a new communication paradigm. Mobile wearable device communications create new challenges compared to ordinary sensor networks and short-range communication. In mobile wearable communications, devices communicate with each other in a peer-to-peer fashion or client-server fashion and also communicate with aggregation points (e.g., smartphones, tablets, and gateway nodes). Wearable devices are expected to integrate multiple radio technologies for various applications' needs with small power consumption and low transmission delays. These devices can hence collect, interpret, transmit, and exchange data among supporting components, other wearable devices, and the Internet. Such data are not limited to people's personal biomedical information but also include human-centric social and contextual data. The success of mobile wearable technology depends on communication and networking architectures that support efficient and secure end-to-end information flows. A key design consideration of future wearable devices is the ability to ubiquitously connect to smartphones or the Internet with very low energy consumption. Radio propagation and, accordingly, channel models are also different from those in other existing wireless technologies. A huge number of connected wearable devices require novel big data processing algorithms, efficient storage solutions, cloud-assisted infrastructures, and spectrum-efficient communications technologies.

A floating point CORDIC based SVD processor

An SVD processor system is presented in which each processing element is implemented using a simple CORDIC unit. The internal recursive loop within the CORDIC module is exploited, with pipelining being used to multiplex the two independent micro-rotations onto a single CORDIC processor. This leads to a high performance and efficient hardware architecture. In addition, a novel method for scale factor correction is presented which only need be applied once at the end of the computation. This also reduces the computation time. The net result is an SVD architecture based on a conventional CORDIC approach, which combines high performance with high silicon area efficiency.

Application-Level Energy Awareness for OpenMP

Power, and consequently energy, has recently attained first-class system resource status, on par with conventional metrics such as CPU time. To reduce energy consumption, many hardware- and OS-level solutions have been investigated. However, application-level information - which can provide the system with valuable insights unattainable otherwise - was only considered in a handful of cases. We introduce OpenMPE, an extension to OpenMP designed for power management. OpenMP is the de-facto standard for programming parallel shared memory systems, but does not yet provide any support for power control. Our extension exposes (i) per-region multi-objective optimization hints and (ii) application-level adaptation parameters, in order to create energy-saving opportunities for the whole system stack. We have implemented OpenMPE support in a compiler and runtime system, and empirically evaluated its performance on two architectures, mobile and desktop. Our results demonstrate the effectiveness of OpenMPE with geometric mean energy savings across 9 use cases of 15 % while maintaining full quality of service.