Influence of dual incorporation of In and N on the luminescence of GaInNAs/GaAs single quantum wells

The optical properties of above- and below-band-edge transitions have been investigated by incorporating In atoms into GaNAs/GaAs single quantum wells. The experimental results show that with increasing In concentration the interband luminescence is improved and the luminescence intensity below the band edge in GaInNAs/GaAs decreases significantly. An interpretation is given that N atoms are preferable to form a covalent bond with In than with Ga atoms in a GaInNAs alloy, due to the compensation of the atomic-size difference between In and N atoms on the GaAs substrate. The photoreflectance spectra of the GaInNAs/GaAs single quantum well support the assignment of an intrinsic mechanism to the high-energy luminescence peak. (C) 2000 American Institute of Physics. [S0003- 6951(00)01752-6].

Molecular beam epitaxy growth of Iny2Al1-y2As/In0.73Ga0.27As/Iny1Al1-y1As/InP P-HEMTs with enhancement conductivity using an intentional nonlattice-matched buffer layer

Pseudomorphic Iny2Al1-y2As/In0.73Ga0.27As/Iny1Al1-y1As (y1 greater than or equal to 0.52) modulation-doped heterostructures with an intentional nonlattice-matched buffer layer were successfully grown by molecular beam epitaxy on (100)InP substrates. Fourier transform photoluminescence and double crystal x-ray diffraction measurements show a superior crystalline quality in the high In content channel, when In mole fraction increases from y1=0.52 to 0.55 in the Iny1Al1-y1As buffer layer. In this case, an increasing of 16.3% and 23.5% for conductivity (mu xn(s)) and mobility, related to the strain compensation in the In0.73Ga0.27As channel, was achieved, respectively, comparing to the structure containing a well-lattice matched buffer layer. With increasing the mismatch further (y1=0.58), a morphology with cross-hatched pattern was observed due to the onset of a large amount of misfit dislocations, and the electronic characterization is not able to be improved continuously. Because we can realize high quality strained P-HEMTs in a relative wide range of equivalent beam flux (EBF) ratios, the stringent control over the constant EBF is not indispensable on this In-based material system. (C) 1997 American Vacuum Society.

Design of Si-based Electro-optical modulator employed dual capacitors - art. no. 68381B

Electro-optical modulator with dual capacitors is designed and based on this design basic configuration of device is realized in laboratory. Exceeding GHz switching speed and high phase modulation efficiency can be expected with this device.

Parallel optical communication subsystem based on VCSEL - art. no. 67833I

A parallel optical communication subsystem based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The bit error rate of this parallel optical communication subsystem is about 0 under the test by SDH optical transport tester during three hours and eighteen minutes.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

The application of parallel optical transmitter and receiver modules in communication subsystems

A new 12 channels parallel optical transmitter module in which a Vertical Cavity Surface Emitting Laser (VCSEL) has been selected as the optical source is capable of transmitting 37.5Gbps date over hundreds meters. A new 12 channels parallel optical receiver module in which a GaAs PIN (p-intrinsic-n-type) array has been selected as the optical receiver unit is capable of responding to 30Gbps date. A transmission system based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The parallel optical modules and the parallel optical transmission system have passed the test in laboratory.

On the design and simulation of high speed electro-optic modulator based on SOI waveguide MOS dual capacitor structure

zhangdi于2010-03-29批量导入

Electroabsorption-modulated DFB laser integrated with dual-waveguide spot-size converter - art. no. 60200N

A 1.55-mu m ridge DFB laser and electroabsorption modulator monolithically integrated with a buried-ridge-stripe dual-waveguide spot-size converter at the output port for low-loss coupling to a cleaved single-mode optical fiber was fabricated by means of selective area growth, quantum well intermixing and dual-core technologies. These devices exhibit threshold current of 28 mA, side mode suppression ratio of 38.0 dB, 3-dB modulation bandwidth of 12.0 GHz, modulator extinction ratios of 25.0 dB dc. The output beam divergence angles of the spot-size converter in the horizontal and vertical directions are as small as 8.0 degrees x 12.6 degrees, respectively, resulting in 3.2 dB coupling loss with a cleaved single-mode optical fiber.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization

This paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

The Fabrication of Eight-Channel DFB Laser Array Using Sampled Gratings

An eight-channel monolithically integrated complex-coupled distributed-feedback laser array based on sampled gratings has been designed and fabricated. Selective lasing at different wavelengths is obtained. The frequency separation between each adjacent channel is about 200 GHz. The typical threshold current is between 30 and 40 mA. The optical output power of each channel is about 10 mW at an injection current of 100 mA. The continuous tuning of emission wavelength with injected currents is also demonstrated.