Best Node Selection Through Distributed Fast Variable Power Multiple Access

In many wireless applications, it is highly desirable to have a fast mechanism to resolve or select the packet from the user with the highest priority. Furthermore, individual priorities are often known only locally at the users. In this paper we introduce an extremely fast, local-information-based multiple access algorithm that selects the best node in 1.8 to 2.1 slots,which is much lower than the 2.43 slot average achieved by the best algorithm known to date. The algorithm, which we call Variable Power Multiple Access Selection (VP-MAS), uses the local channel state information from the accessing nodes to the receiver, and maps the priorities into the receive power.It is inherently distributed and scales well with the number of users. We show that mapping onto a discrete set of receive power levels is optimal, and provide a complete characterization for it. The power levels are chosen to exploit packet capture that inherently occurs in a wireless physical layer. The VP-MAS algorithm adjusts the expected number of users that contend in each step and their respective transmission powers, depending on whether previous transmission attempts resulted in capture,idle channel, or collision.

An Adaptive Feature Based Low Power Motion Estimation Algorithm

Motion Estimation is one of the most power hungry operations in video coding. While optimal search (eg. full search)methods give best quality, non optimal methods are often used in order to reduce cost and power. Various algorithms have been used in practice that trade off quality vs. complexity. Global elimination is an algorithm based on pixel averaging to reduce complexity of motion search while keeping performance close to that of full search. We propose an adaptive version of the global elimination algorithm that extracts individual macro-block features using Hadamard transform to optimize the search. Performance achieved is close to the full search method and global elimination. Operational complexity and hence power is reduced by 30% to 45% compared to global elimination method.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

WEPA: Wind energy potential assessment-spatial decision support system

Spatial Decision Support System (SDSS) assist in strategic decision-making activities considering spatial and temporal variables, which help in Regional planning. WEPA is a SDSS designed for assessment of wind potential spatially. A wind energy system transforms the kinetic energy of the wind into mechanical or electrical energy that can be harnessed for practical use. Wind energy can diversify the economies of rural communities, adding to the tax base and providing new types of income. Wind turbines can add a new source of property value in rural areas that have a hard time attracting new industry. Wind speed is extremely important parameter for assessing the amount of energy a wind turbine can convert to electricity: The energy content of the wind varies with the cube (the third power) of the average wind speed. Estimation of the wind power potential for a site is the most important requirement for selecting a site for the installation of a wind electric generator and evaluating projects in economic terms. It is based on data of the wind frequency distribution at the site, which are collected from a meteorological mast consisting of wind anemometer and a wind vane and spatial parameters (like area available for setting up wind farm, landscape, etc.). The wind resource is governed by the climatology of the region concerned and has large variability with reference to space (spatial expanse) and time (season) at any fixed location. Hence the need to conduct wind resource surveys and spatial analysis constitute vital components in programs for exploiting wind energy. SDSS for assessing wind potential of a region / location is designed with user friendly GUI’s (Graphic User Interface) using VB as front end with MS Access database (backend). Validation and pilot testing of WEPA SDSS has been done with the data collected for 45 locations in Karnataka based on primary data at selected locations and data collected from the meteorological observatories of the India Meteorological Department (IMD). Wind energy and its characteristics have been analysed for these locations to generate user-friendly reports and spatial maps. Energy Pattern Factor (EPF) and Power Densities are computed for sites with hourly wind data. With the knowledge of EPF and mean wind speed, mean power density is computed for the locations with only monthly data. Wind energy conversion systems would be most effective in these locations during May to August. The analyses show that coastal and dry arid zones in Karnataka have good wind potential, which if exploited would help local industries, coconut and areca plantations, and agriculture. Pre-monsoon availability of wind energy would help in irrigating these orchards, making wind energy a desirable alternative.

Power Efficient Redundant Execution for Chip Multiprocessor

This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1:2%

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.