Social networks applied to training

In this article, we address the importance and relevance that social networks exhibit in their use as an educational resource.  This relevance relies in the possibility of implementing new learning resources or increasing the level of the participant's connectivity, as well as developing learning communities.  Also, the risk entailed from their use is discussed, especially for the students that have a low technological education or those having excessive confidence on the media.  It is important to highlight that the educational use of social networks is not a simple extension or translation of the student's habitual, recreational use, but that it implies an important change in the roles given to teachers as well as learners; from accommodative learning environments that only encourage memorization to other environments that demand an active, reflective, collaborative and proactive attitude, that require the development/acquisition of technological as well as social abilities, aptitudes and values.  It is also important to highlight that a correct implementation and adequate use will not only foment formal learning, but also informal and non-formal learning.

Extension of the Ye and Shreeve group contribution method for density estimation of ionic liquids in a wide range of temperatures and pressures

An extension of the Ye and Shreeve group contribution method [C. Ye, J.M. Shreeve, J. Phys. Chem. A 111 (2007) 1456–1461] for the estimation of densities of ionic liquids (ILs) is here proposed. The new version here presented allows the estimation of densities of ionic liquids in wide ranges of temperature and pressure using the previously proposed parameter table. Coefficients of new density correlation proposed were estimated using experimental densities of nine imidazolium-based ionic liquids. The new density correlation was tested against experimental densities available in literature for ionic liquids based on imidazolium, pyridinium, pyrrolidinium and phosphonium cations. Predicted densities are in good agreement with experimental literature data in a wide range of temperatures (273.15–393.15 K) and pressures (0.10–100 MPa). For imidazolium-based ILs, the mean percent deviation (MPD) is 0.45% and 1.49% for phosphonium-based ILs. A low MPD ranging from 0.41% to 1.57% was also observed for pyridinium and pyrrolidinium-based ILs.

On linear extension operators

We construct a countable-dimensional Hausdorff locally convex topological vector space $E$ and a stratifiable closed linear subspace $F$ subset of $E$ such that any linear extension operator from $C_b(F)$ to $C_b(E)$ is unbounded (here $C_b(X)$ stands for the Banach space of continuous bounded real-valued functions on $X$).

An adaptable and scalable asymmetric cryptographic processor

In this paper a novel scalable public-key processor architecture is presented that supports modular exponentiation and Elliptic Curve Cryptography over both prime GF(p) and binary GF(2) extension fields. This is achieved by a high performance instruction set that provides a comprehensive range of integer and polynomial basis field arithmetic. The instruction set and associated hardware are generic in nature and do not specifically support any cryptographic algorithms or protocols. Firmware within the device is used to efficiently implement complex and data intensive arithmetic. A firmware library has been developed in order to demonstrate support for numerous exponentiation and ECC approaches, such as different coordinate systems and integer recoding methods. The processor has been developed as a high-performance asymmetric cryptography platform in the form of a scalable Verilog RTL core. Various features of the processor may be scaled, such as the pipeline width and local memory subsystem, in order to suit area, speed and power requirements. The processor is evaluated and compares favourably with previous work in terms of performance while offering an unparalleled degree of flexibility. © 2006 IEEE.

Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.