High-efficiency low-voltage-stress Class-EF PA with extended maximum operating frequency

The Class-EF power amplifier (PA) introduced recently has a peak switch voltage much lower than the well-known Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. As a result, softswitching operation that minimizes power dissipation during OFF-to-ON transient cannot be achieved at high frequencies. A novel Class-EF topology with transmission-line load network proposed in this paper allows the PA to operate at much higher frequencies without trading the other figures of merit. Closed-form formulations are derived to simultaneously satisfy the Class-EF impedances requirement at fundamental frequency, all even harmonics, and the first two odd harmonics as well as to provide matching to 50O load. © 2011 Institut fur Mikrowellen.

Full duplex reflection amplifier tag

The authors describe a reflection amplifier adapted to have both a reflection and a transmission port. The amplifier uses a single silicon bipolar transistor and demonstrates a reflection gain of 13 dB, transmission gain of 10 dB and 3.4 dB noise figure at 5.25 GHz. The added feature of transmission gain in the reflection amplifier permits practical implementation of full duplex microwave radiofrequency indentification (RFID) tag operation. By using a simple subcarrier modulation scheme full duplex RFID operation utilising this amplifier is demonstrated. These results indicate that for 27 dBm (0.5 W) effective isotropic radiated power (EIRP) transmit power it should be possible to obtain approximately 8 m downlink range and 25 m uplink range

Coleoptera and microbe biomass in Antarctic Dry Valley paleosols adjacent to the Inland Ice: Implications for Mars

Bulk paleosol samples collected from a Middle to Early Miocene moraine in the New Mountain area of the Dry Valleys, Antarctica, yielded Coleoptera exoskeletons and occasional endoskeletons showing considerable diagenetic effects along with several species of bacteria, all lodged in a dry-frozen but salt-rich horizon at shallow depth to the land surface. The till is at the older end of a chronologic sequence of glacial deposits, thought to have been deposited before the transition from wet-based to cold-based ice (similar to 15 Ma), and hence, entirely weathered in contact with the subaerial atmosphere. It is possible, though not absolutely verifiable, that the skeletons date from this early stage of emplacement having undergone modifications whenever light snowmelt occurred or salt concentrations lowered the freezing temperature to maintain water as liquid. Correlation of the Coleoptera species with cultured bacteria in the sample and the likelihood of co-habitation with Beauveria bassiani found in two adjacent, although younger paleosols, leads to new questions about the antiquity of the Coleoptera and the source of N and glucose from chitinase derived from the insects. The skeletons in the 831 section may date close to the oldest preserved chitin (Oligocene) yet found on Earth. While harsh Martian conditions make it seemingly intolerable for complex, multicellular organisms such as insects to exist in the near-surface and subaerially, life within similar cold, dry paleosol microenvironments (Cryosols) of Antarctica point to life potential for the Red Planet, especially when considering the relatively diverse microbe (bacteria and fungi) population. (C) 2011 Elsevier Ltd. All rights reserved.

Synchronized phasor measurement on the All-Ireland electrical network

Variations in the phase angle difference between a remote 11kV connected wind farm and the centre of Belfast during a typical working day are investigated in the paper. The results obtained using phasor measurement units (PMUs) are compared with the data generated using a PSS/E simulator configured to model the N.Ireland network. The study investigates the effect of changes in the load demand and the wind farm output power on the phase angles at various locations on the network. The paper finally describes how a major system disturbance on the All-Ireland network was monitored and analysed using PMUs located at Queen's University, Belfast and University College Dublin. ©2007 IEEE.

Coordinated Design of Phase Measurement Unit and Power System Stabilisers in Large Scale Power System

This paper presents a case-study of a PMU application with PSS support in a real large scale Chinese power system to suppress inter-area oscillations. The paper uses PMU measured feedback signals from a PSS input signal for dynamic torque analysis (DTA). In the paper, a mathematical model of multi-machine power system is described, followed by formation of the residue and DTA indices. Simulations of the model are used with a large-scale power system model to demonstrate the role of PSS and the equivalence of DTA residue indices.

Intermittency, quasiperiodicity and chaos in probe-induced ferroelectric domain switching

Memristive materials and devices, which enable information storage and processing on one and the same physical platform, offer an alternative to conventional von Neumann computation architectures. Their continuous spectra of states with intricate field-history dependence give rise to complex dynamics, the spatial aspect of which has not been studied in detail yet. Here, we demonstrate that ferroelectric domain switching induced by a scanning probe microscopy tip exhibits rich pattern dynamics, including intermittency, quasiperiodicity and chaos. These effects are due to the interplay between tip-induced polarization switching and screening charge dynamics, and can be mapped onto the logistic map. Our findings may have implications for ferroelectric storage, nanostructure fabrication and transistor-less logic.

Development and assessment of a robust optimization metric for WAMPAC modeling

A PMU based WAMS is to be placed on a weakly coupled section of distribution grid, with high levels of distributed generation. In anticipation of PMU data a Siemens PSS/E model of the electrical environment has been used to return similar data to that expected from the WAMS. This data is then used to create a metric that reflects optimization, control and protection in the region. System states are iterated through with the most desirable one returning the lowest optimization metric, this state is assessed against the one returned by PSS/E under normal circumstances. This paper investigates the circumstances that trigger SPS in the region, through varying generation between 0 and 110% and compromising the network through line loss under summer minimum and winter maximum conditions. It is found that the optimized state can generally tolerate an additional 2 MW of generation (3% of total) before encroaching the same thresholds and in one instance moves the triggering to 100% of generation output.

ASIP: developments, challenges and trends

Application Specific Instruction Set Processor (ASIP) becomes an attractive substitute for ASIC as transistor density, logic complexity and market competition boost. Similar to ASIC, ASIP is based on customized and tailored architectures. In this way, ASIP delivers high performances with low overheads on cost and power whilst taking the advantages of high flexibility and fast time-to-market as a processor-based solution. To demonstrate this effective solution for embedded applications, this paper performs an overall investigation on ASIP's developments, challenges, trends in terms of architectures and design methodologies.

Long-Range Lateral Dopant Diffusion in Tungsten Silicide Layers

Novel diode test structures have been manufactured to characterize long-range dopant diffusion in tungsten silicide layers. A tungsten silicide to p-type silicon contact has been characterized as a Schottky barrier rectifying contact with a silicide work function of 4.8 eV. Long-range diffusion of boron for an anneal at 900 °C for 30 min has been shown to alter this contact to become ohmic. Long-range diffusion of phosphorus with a similar anneal alters the contact to become a bipolar n-p diode. Bipolar diode action is demonstrated experimentally for anneal schedules of 30 min at 900 °C, indicating long-range diffusion of phosphorus (~38 µm), SIMS analysis shows dopant redistribution is adversely affected by segregation to the silicide/oxide interface. The concept of conduit diffusion has been demonstrated experimentally for application in advanced bipolar transistor technology. © 2009 IEEE.

Il Piano della Performance nei Comuni medi. La proposta di una nuova configurazione per superare l’inadeguatezza delle prime applicazioni

Il D.Lgs. 150/09 ha inteso dar vita ad una “riforma organica” della PA italiana, improntandone il funzionamento a logiche di programmazione e controllo delle performance. Attorno a tale concetto la riforma ha costruito un Sistema teso a programmare, misurare, controllare, valutare e comunicare la performance degli enti. Il lavoro si focalizza sulla programmazione, e in particolare sullo strumento cardine introdotto dal D.Lgs. 150/09: il Piano della Performance (PdP). Il contributo, basato su una metodologia deduttivo-induttiva, si concentra sui comuni medi italiani, scelti in quanto statisticamente rappresentativi del livello medio di complessità degli enti locali. Sono stati oggetto di indagine i PdP pubblicati sui siti istituzionali degli enti considerati, al fine di verificarne sia il livello di aderenza alle Linee Guida (LG) emanate dalla Commissione Indipendente per la Valutazione, la Trasparenza e l’Integrità delle amministrazioni pubbliche (CIVIT) e dalla Associazione Nazionale Comuni Italiani (ANCI), sia il loro livello di adeguatezza economico-aziendale. Preliminarmente si indagherà il tema della programmazione, sotto il profilo normativo-dottrinale, concentrandosi su soggetti, processi e strumenti. Poi si sposterà il focus sul PdP: dopo aver definito obiettivi, quesiti e metodologia della ricerca, verranno esplicitate le configurazioni di PdP emergenti dalle LG CIVIT e ANCI. Verranno poi illustrati i risultati della ricerca empirica, mettendo in luce il livello di allineamento dei PdP dei comuni medi alle LG, nonché il livello di adeguatezza economico-aziendale degli stessi. Si tratteggeranno quindi alcune brevi conclusioni.

A 2.2 GHz High-Efficiency Third-Harmonic-Peaking Class-EF Power Amplifier

This paper presents the design and implementation of a low-voltage-stress Class-EF power amplifier (PA) with extended maximum operating frequency, named as ‘third-harmonic-peaking Class-EF PA’. A novel transmission-line load network is proposed to meet the Class-EF impedance requirements at the fundamental, all even harmonics, and third harmonic components. It also provides an impedance matching to a 50 Ω load. A more effective λ/8 open- and shorted-stub network is deployed at the drain of the transistor replacing the traditional λ/4 transmission line. Implemented using GaN HEMTs, the PA delivered 39.2 dBm output power with 80.5% drain efficiency and 71% PAE at 2.22 GHz.

On the potential of significance-driven execution for energy-aware HPC

Dynamic Voltage and Frequency Scaling (DVFS) exhibits fundamental limitations as a method to reduce energy consumption in computing systems. In the HPC domain, where performance is of highest priority and codes are heavily optimized to minimize idle time, DVFS has limited opportunity to achieve substantial energy savings. This paper explores if operating processors Near the transistor Threshold Volt- age (NTV) is a better alternative to DVFS for break- ing the power wall in HPC. NTV presents challenges, since it compromises both performance and reliability to reduce power consumption. We present a first of its kind study of a significance-driven execution paradigm that selectively uses NTV and algorithmic error tolerance to reduce energy consumption in performance- constrained HPC environments. Using an iterative algorithm as a use case, we present an adaptive execution scheme that switches between near-threshold execution on many cores and above-threshold execution on one core, as the computational significance of iterations in the algorithm evolves over time. Using this scheme on state-of-the-art hardware, we demonstrate energy savings ranging between 35% to 67%, while compromising neither correctness nor performance.

Voltage over-scaling:A cross-layer design perspective for energy efficient systems

Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.