955 resultados para Transistor circuits.


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This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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A simplified yet analytical approach on few ballistic properties of III-V quantum wire transistor has been presented by considering the band non-parabolicity of the electrons in accordance with Kane's energy band model using the Bohr-Sommerfeld's technique. The confinement of the electrons in the vertical and lateral directions are modeled by an infinite triangular and square well potentials respectively, giving rise to a two dimensional electron confinement. It has been shown that the quantum gate capacitance, the drain currents and the channel conductance in such systems are oscillatory functions of the applied gate and drain voltages at the strong inversion regime. The formation of subbands due to the electrical and structural quantization leads to the discreetness in the characteristics of such 1D ballistic transistors. A comparison has also been sought out between the self-consistent solution of the Poisson's-Schrodinger's equations using numerical techniques and analytical results using Bohr-Sommerfeld's method. The results as derived in this paper for all the energy band models gets simplified to the well known results under certain limiting conditions which forms the mathematical compatibility of our generalized theoretical formalism.

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The implementation of three-phase sinusoidal pulse-width-modulated inverter control strategy using microprocessor is discussed in this paper. To save CPU time, the DMA technique is used for transferring the switching pattern from memory to the pulse amplifier and isolation circuits of individual thyristors in the inverter bridge. The method of controlling both voltage and frequency is discussed here.

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Negative impedance converters (NIC's) may be used to realize negative driving-point impedances. The effect of the nonideal characteristics of the operational amplifier such as finite frequencydependent gain and output impedance on the performance of the negative impedances is analyzed. Detailed equivalent circuits showing the additional positive or negative inductive impedances due to the nonideal characteristics are given for negative resistance and negative capacitance realizations, and their relative performances are compared. The experimental results confirm the validity of the equivalent circuits. The effect of the slew rate of the operational amplifier on the maximum signal-handling capability (SHC) of the negative impedances at high frequencies is studied. Practical design considerations for achieving wider bandwidth as well as improved SHC are discussed.

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The recent trend towards minimizing the interconnections in large scale integration (LSI) circuits has led to intensive investigation in the development of ternary circuits and the improvement of their design. The ternary multiplexer is a convenient and useful logic module which can be used as a basic building block in the design of a ternary system. This paper discusses a systematic procedure for the simplification and realization of ternary functions using ternary multiplexers as building blocks. Both single level and multilevel multiplexing techniques are considered. The importance of the design procedure is highlighted by considering two specific applications, namely, the development of ternary adder/subtractor and TCD to ternary converter.

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An efficient measurement technique for studying the effect of transient electromagnetic fields under controlled conditions has been described. Broad-band TEM fields with a rise-time of a few nanoseconds were generated using a stripline method. Theoretical results are obtained and experimental measurements which confirm these results are described. The work will form the basis for a study of the susceptibility of digital integrated circuits and their interconnections to transient electromagnetic fields.

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The departures of the operational amplifiers (OA's) from the ideal performance and their effect on VCV's in the inverting and noninverting mode are discussed. It is found that for the same ideal gain, the bandwidths for the inverting and noninverting modes are different, the former being less. Complete equivalent circuits describing the frequency dependance of the input and output impedances for both modes are given. In particular, the output impedance is shown to be inductive for the frequencies of interest, and this is also confirmed by experimental results.

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The deviation in the performance of active networks due to practical operational amplifiers (OA) is mainly because of the finite gain bandwidth productBand nonzero output resistanceR_0. The effect ofBandR_0on two OA impedances and single and multi-OA filters are discussed. In filters, the effect ofR_0is to add zeros to the transfer function often making it nonminimum phase. A simple method of analysis has been suggested for 3-OA biquad and coupled biquad circuits. A general method of noise minimization of the generalized impedance converter (GIC), while operating OA's within the prescribed voltage and current limits, is also discussed. The 3-OA biquadratic sections analyzed also exhibit noise behavior and signal handling capacity similar to the GIC. The GIC based structures are found to be better than other configurations both in biquadratic sections and direct realizations of higher order transfer functions.

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Doping graphene with electron donating or accepting molecules is an interesting approach to introduce carriers into it, analogous to electrochemical doping accomplished in graphene when used in a field-effect transistor. Here, we use first-principles density-functional theory to determine changes in the electronic-structure and vibrational properties of graphene that arise from the adsorption of aromatic molecules such as aniline and nitrobenzene. Identifying the roles of various mechanisms of chemical interaction between graphene and a molecule, we bring out the contrast between electrochemical and molecular doping of graphene. Our estimates of various contributions to shifts in the Raman-active modes of graphene with molecular doping are fundamental to the possible use of Raman spectroscopy in (a) characterization of the nature and concentration of carriers in graphene with molecular doping, and (b) graphene-based chemical sensors.

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In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose Static Noise Margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and Hold Noise Margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag-super-cut-off in stand-by mode without affecting its performance in active mode of operation. The Read Bit Line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

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A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT). It is shown that choosing alpha=CT/CG=1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to plusmn0.03 e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that a isin [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.

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Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current (IOFF), its practical application is questionable due to low ON current (ION) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in ION. The enhancement in ION is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An ION of View the MathML source and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the IOFF in fA range.

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Four hybrid algorithms has been developed for the solution of the unit commitment problem. They use simulated annealing as one of the constituent techniques, and produce lower cost schedules; two of them have less overhead than other soft computing techniques. They are also more robust to the choice of parameters. A special technique avoids the generating of infeasible schedules, and thus reduces computation time.