Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Distributed Region-Based Memory Allocation and Synchronization

We present DRASync, a region-based allocator that implements a global address space abstraction for MPI programs with pointer-based data structures. The main features of DRASync are: (a) it amortizes communication among nodes to allow efficient parallel allocation in a global address space; (b) it takes advantage of bulk deallocation and good locality with pointer-based data structures; (c) it supports ownership semantics of regions by nodes akin to reader–writer locks, which makes for a high-level, intuitive synchronization tool in MPI programs, without sacrificing message-passing performance. We evaluate DRASync against a state-of-the-art distributed allocator and find that it produces comparable performance while offering a higher-level abstraction to programmers.

A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

Competition between memory-keeping and memory-erasing decoherence channels

We study the competing effects of simultaneous Markovian and non-Markovian decoherence mechanisms acting on a single spin. We show the existence of a threshold in the relative strength of such mechanisms above which the spin dynamics becomes fully Markovian, as revealed by the use of several non-Markovianity measures. We identify a measure-dependent nested structure of such thresholds, hinting at a causality relationship among the various non-Markovianity witnesses used in our analysis. Our considerations are then used to argue the unavoidably non-Markovian evolution of a single-electron quantum dot exposed to both intrinsic and Markovian technical noise, the latter of arbitrary strength. 

Cyclic nanoindentation and nano-impact fatigue characterisation of functionally graded TiN/TiNi shape memory film

This paper investigates the mechanism of nanoscale fatigue of functionally graded TiN/TiNi films using nano-impact and multiple-loading-cycle nanoindentation tests. The functionally graded films were deposited on silicon substrate, in which TiNi films maintain shape memory and pseudo elastic behavior, while a modified TiN surface layer provides tribological and anti-corrosion properties. Nanomechanical tests were performed to comprehend the localized film performance and failure modes of the functionally graded film using NanoTestTM equipped with Berkovich and conical indenter between 100 μN to 500 mN loads. The loading mechanism and load history are critical to define film failure modes (i.e. backward depth deviation) including the shape memory effect of the functionally graded layer. The results are sensitive to the applied load, loading type (e.g. semi-static, dynamic) and probe geometry. Based on indentation force-depth profiles, depth-time data and post-test surface observations of films, it is concluded that the shape of the nanoindenter is critical in inducing the localized indentation stress and film failure, including shape recovery at the lower load range. Elastic-plastic finite element (FE) simulation during nanoindentation loading indicated that the location of subsurface maximum stress near the interface influences the backward depth deviation type of film failure. A standalone, molecular dynamics simulation was performed with the help of a long range potential energy function to simulate the tensile test of TiN nanowire with two different aspect ratios to investigate the theory of its failure mechanism.

Post-Conflict Performance, Film and Visual Arts:Cities of Memory

This book examines how contemporary theatre, performance, film and the visual arts respond to the post-conflict condition. The contents of the volume focus on a range of post-conflict cities, encouraging interdisciplinary discussion on the role of the arts and its relation to issues of testimony, witnessing, forgetting, representation, healing, reconciliation, agency, and metaphor. Contributors include: Thomas Elsaesser, Jane Taylor, Marvin Carlson, Rob Stone, Laurel Borisenko, Katarzyna Puzon, Miriam Paeslack, Emma Grey, Paula Blair, Zoran Poposki, Marija Todorova, Elena Carduro, and Paul Devlin.

Software-Managed Energy-Efficient Hybrid DRAM/NVM Main Memory

This paper evaluates the viability of user-level software management of a hybrid DRAM/NVM main memory system. We propose an operating system (OS) and programming interface to place data from within the user application. We present a profiling tool to help programmers decide on the placement of application data in hybrid memory systems. Cycle-accurate simulation of modified applications confirms that our approach is more energy-efficient than state-of-the- art hardware or OS approaches at equivalent performance. Moreover, our results are validated on several candidate NVM technologies and a wide set of 14 benchmarks.
The key observation behind this work is that, for the work- loads we evaluated, application objects are too short-lived to motivate migration. Utilizing this property significantly reduces the hardware complexity of hybrid memory systems.

On the complexity of solving polytree-shaped limited memory influence diagrams with binary variables

Influence diagrams are intuitive and concise representations of structured decision problems. When the problem is non-Markovian, an optimal strategy can be exponentially large in the size of the diagram. We can avoid the inherent intractability by constraining the size of admissible strategies, giving rise to limited memory influence diagrams. A valuable question is then how small do strategies need to be to enable efficient optimal planning. Arguably, the smallest strategies one can conceive simply prescribe an action for each time step, without considering past decisions or observations. Previous work has shown that finding such optimal strategies even for polytree-shaped diagrams with ternary variables and a single value node is NP-hard, but the case of binary variables was left open. In this paper we address such a case, by first noting that optimal strategies can be obtained in polynomial time for polytree-shaped diagrams with binary variables and a single value node. We then show that the same problem is NP-hard if the diagram has multiple value nodes. These two results close the fixed-parameter complexity analysis of optimal strategy selection in influence diagrams parametrized by the shape of the diagram, the number of value nodes and the maximum variable cardinality.

Solving Limited Memory Influence Diagrams

We present a new algorithm for exactly solving decision making problems represented as influence diagrams. We do not require the usual assumptions of no forgetting and regularity; this allows us to solve problems with simultaneous decisions and limited information. The algorithm is empirically shown to outperform a state-of-the-art algorithm on randomly generated problems of up to 150 variables and 10^64 solutions. We show that these problems are NP-hard even if the underlying graph structure of the problem has low treewidth and the variables take on a bounded number of states, and that they admit no provably good approximation if variables can take on an arbitrary number of states.

Solving Limited Memory Influence Diagrams

We present a new algorithm for exactly solving decision making problems represented as influence diagrams. We do not require the usual assumptions of no forgetting and regularity; this allows us to solve problems with simultaneous decisions and limited information. The algorithm is empirically shown to outperform a state-of-the-art algorithm on randomly generated problems of up to 150 variables and 10^64 solutions. We show that the problem is NP-hard even if the underlying graph structure of the problem has small treewidth and the variables take on a bounded number of states, but that a fully polynomial time approximation scheme exists for these cases. Moreover, we show that the bound on the number of states is a necessary condition for any efficient approximation scheme.