Understanding the critical distance in sparse distributed memory

Modelos de tomada de decisão necessitam refletir os aspectos da psi- cologia humana. Com este objetivo, este trabalho é baseado na Sparse Distributed Memory (SDM), um modelo psicologicamente e neuro- cientificamente plausível da memória humana, publicado por Pentti Kanerva, em 1988. O modelo de Kanerva possui um ponto crítico: um item de memória aquém deste ponto é rapidamente encontrado, e items além do ponto crítico não o são. Kanerva calculou este ponto para um caso especial com um seleto conjunto de parâmetros (fixos). Neste trabalho estendemos o conhecimento deste ponto crítico, através de simulações computacionais, e analisamos o comportamento desta “Critical Distance” sob diferentes cenários: em diferentes dimensões; em diferentes números de items armazenados na memória; e em diferentes números de armazenamento do item. Também é derivada uma função que, quando minimizada, determina o valor da “Critical Distance” de acordo com o estado da memória. Um objetivo secundário do trabalho é apresentar a SDM de forma simples e intuitiva para que pesquisadores de outras áreas possam imaginar como ela pode ajudá-los a entender e a resolver seus problemas.

Implementação em hardware de uma Rede Neuronal com ummicroprocessador embebido em FPGA

O objectivo deste trabalho é a implementação em hardware de uma Rede Neuronal com um microprocessador embebido, podendo ser um recurso valioso em várias áreas científicas. A importância das implementações em hardware deve-se à flexibilidade, maior desempenho e baixo consumo de energia. Para esta implementação foi utilizado o dispositivo FPGA Virtex II Pro XC2VP30 com um MicroBlaze soft core, da Xilinx. O MicroBlaze tem vantagens como a simplicidade no design, sua reutilização e fácil integração com outras tecnologias. A primeira fase do trabalho consistiu num estudo sobre o FPGA, um sistema reconfigurável que possui características importantes como a capacidade de executar em paralelo tarefas complexas. Em seguida, desenvolveu-se o código de implementação de uma Rede Neuronal Artificial baseado numa linguagem de programação de alto nível. Na implementação da Rede Neuronal aplicou-se, na camada escondida, a função de activação tangente hiperbólica, que serve para fornecer a não linearidade à Rede Neuronal. A implementação é feita usando um tipo de Rede Neuronal que permite apenas ligações no sentido de saída, chamado Redes Neuronais sem realimentação (do Inglês Feedforward Neural Networks - FNN). Como as Redes Neuronais Artificiais são sistemas de processamento de informações, e as suas características são comuns às Redes Neuronais Biológicas, aplicaram-se testes na implementação em hardware e analisou-se a sua importância, a sua eficiência e o seu desempenho. E finalmente, diante dos resultados, fez-se uma análise de abordagem e metodologia adoptada e sua viabilidade.

Sincronização de múltiplas câmaras e controlo de iluminação sobre uma plataforma FPGA

O objetivo deste projeto foi o de realizar a sincronização de pelo menos quatro câmaras individuais, ajustando dinamicamente o frame rate de operação de cada câmara, tendo por base a família de sensores de imagem CMOS NanEye da empresa Awaiba, numa plataforma FPGA com interface USB3. Durante o projeto analisou-se, com a assistência de um supervisor da Awaiba, o sistema core de captura de imagem existente, baseado em VHDL. Foi estudado e compreendido o princípio do ajuste dinâmico do frame rate das câmaras. Tendo sido então desenvolvido o módulo de controlo da câmara, em VHDL, e um algoritmo de ajuste dinâmico do frame rate, sendo este implementado junto com a plataforma de processamento e interface da FPGA. Foi criado um módulo para efetuar a monitorização da frequência de operação de cada câmara, medindo o período de cada linha numa frame, tendo por base um sinal de relógio de valor conhecido. A frequência é ajustada variando o nível de tensão aplicado ao sensor com base no erro entre o período da linha medido e o período pretendido. Para garantir o funcionamento conjunto de múltiplas câmaras em modo síncrono foi implementada uma interface Master-Slave entre estas. Paralelamente ao módulo anteriormente descrito, implementou-se um sistema de controlo automático de iluminação com base na análise de regiões de interesse em cada frame captada por uma câmara NanEye. A intensidade de corrente aplicada às fontes de iluminação acopladas à câmara é controlada dinamicamente com base no nível de saturação dos pixéis analisados em cada frame. Foram desenvolvidas e implementadas variantes do algoritmo de controlo e o seu desempenho foi avaliado em laboratório. Os resultados obtidos na prática evidenciam que a solução implementada cumpre os requisitos de controlo e ajuste da frequência de operação de múltiplas câmaras. Mostrou ser um método de controlo capaz de manter um erro de sincronização médio de 3,77 μs mesmo na presença de variações de temperatura de aproximadamente 50 °C. Foi também demonstrado que o sistema de controlo de iluminação é capaz de proporcionar uma experiência de visualização adequada, alcançando erros menores que 3% e uma velocidade de ajuste máxima inferior a 1 s.

A Mismatch-Based Model for Memory Reconsolidation and Extinction in Attractor Networks

OSAN, R. , TORT, A. B. L. , AMARAL, O. B. . A mismatch-based model for memory reconsolidation and extinction in attractor networks. Plos One, v. 6, p. e23113, 2011.

Increased hippocampal excitability and impaired spatial memory function in mice lacking VGLUT2 selectively in neurons defined by tyrosine hydroxylase promoter activity

Three populations of neurons expressing the vesicular glutamate transporter 2 (Vglut2) were recently described in the A10 area of the mouse midbrain, of which two populations were shown to express the gene encoding, the rate-limiting enzyme for catecholamine synthesis, tyrosine hydroxylase (TH).One of these populations (‘‘TH– Vglut2 Class1’’) also expressed the dopamine transporter (DAT) gene while one did not ("TH–Vglut2 Class2"), and the remaining population did not express TH at all ("TH-Vglut2-only"). TH is known to be expressed by a promoter which shows two phases of activation, a transient one early during embryonal development, and a later one which gives rise to stable endogenous expression of the TH gene. The transient phase is, however, not specific to catecholaminergic neurons, a feature taken to advantage here as it enabled Vglut2 gene targeting within all three A10 populations expressing this gene, thus creating a new conditional knockout. These knockout mice showed impairment in spatial memory function. Electrophysiological analyses revealed a profound alteration of oscillatory activity in the CA3 region of the hippocampus. In addition to identifying a novel role for Vglut2 in hippocampus function, this study points to the need for improved genetic tools for targeting of the diversity of subpopulations of the A10 area

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing

Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

Implementação de processador banda base ofdma para downlink lte em fpga

This work treats of an implementation OFDMA baseband processor in hardware for LTE Downlink. The LTE or Long Term Evolution consist the last stage of development of the technology called 3G (Mobile System Third Generation) which offers an increasing in data rate and more efficiency and flexibility in transmission with application of advanced antennas and multiple carriers techniques. This technology applies in your physical layer the OFDMA technical (Orthogonal Frequency Division Multiple Access) for generation of signals and mapping of physical resources in downlink and has as base theoretical to OFDM multiple carriers technique (Orthogonal Frequency Division Multiplexing). With recent completion of LTE specifications, different hardware solutions have been developed, mainly, to the level symbol processing where the implementation of OFDMA processor in base band is commonly considered, because it is also considered a basic architecture of others important applications. For implementation of processor, the reconfigurable hardware offered by devices as FPGA are considered which shares not only to meet the high requirements of flexibility and adaptability of LTE as well as offers possibility of an implementation quick and efficient. The implementation of processor in reconfigurable hardware meets the specifications of LTE physical layer as well as have the flexibility necessary for to meet others standards and application which use OFDMA processor as basic architecture for your systems. The results obtained through of simulation and verification functional system approval the functionality and flexibility of processor implemented

Projeto em FPGA de um controlador unificado para correção de fator de potência em retificadores boost bidirecionais monofásicos

The use of Field Programmable Gate Array (FPGA) for development of digital control strategies for power electronics applications has aroused a growing interest of many researchers. This interest is due to the great advantages offered by FPGA, which include: lower design effort, high performance and highly flexible prototyping. This work proposes the development and implementation of an unified one-cycle controller for boost CFP rectifier based on FPGA. This controller can be applied to a total of twelve converters, six inverters and six rectifiers defined by four single phase VSI topologies and three voltage modulation types. The topologies considered in this work are: full-bridge, interleaved full-bridge, half-bridge and interleaved half-bridge. While modulations are classified in bipolar voltage modulation (BVM), unipolar voltage modulation (UVM) and clamped voltage modulation (CVM). The proposed project is developed and prototyped using tools Matlab/Simulink® together with the DSP Builder library provided by Altera®. The proposed controller was validated with simulation and experimental results

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

Modeling and Experimental Aspects of Self-healing Bolted Joint through Shape Memory Alloy Actuators

Bolted joints are a form of mechanical coupling largely used in machinery due to their reliability and low cost. Failure of bolted joints can lead to catastrophic events, such as leaking, train derailments, aircraft crashes, etc. Most of these failures occur due to the reduction of the pre-load, induced by mechanical vibration or human errors in the assembly or maintenance process. This article investigates the application of shape memory alloy (SMA) washers as an actuator to increase the pre-load on loosened bolted joints. The application of SMA washer follows a structural health monitoring procedure to identify a damage (reduction in pre-load) occurrence. In this article, a thermo-mechanical model is presented to predict the final pre-load achieved using this kind of actuator, based on the heat input and SMA washer dimension. This model extends and improves on the previous model of Ghorashi and Inman [2004, "Shape Memory Alloy in Tension and Compression and its Application as Clamping Force Actuator in a Bolted Joint: Part 2 - Modeling," J. Intell. Mater. Syst. Struct., 15:589-600], by eliminating the pre-load term related to nut turning making the system more practical. This complete model is a powerful but complex tool to be used by designers. A novel modeling approach for self-healing bolted joints based on curve fitting of experimental data is presented. The article concludes with an experimental application that leads to a change in joint assembly to increase the system reliability, by removing the ceramic washer component. Further research topics are also suggested.

H1 but not H2 histamine antagonist receptors mediate anxiety-related behaviors and emotional memory deficit in mice subjected to elevated plus-maze testing

This study investigated the role of H1 and H2 receptors in anxiety and the retrieval of emotional memory using a Trial 1/Trial 2 (T1/T2) protocol in an elevated plus-maze (EPM). Tests were performed on 2 consecutive days, designated T1 and T2. Before T1, the mice received intraperitoneal injections of saline (SAL), 20 mg/kg zolantidine (ZOL, an H2 receptor antagonist), or 8.0 or 16 mg/kg chlorpheniramine (CPA, an H1 receptor antagonist). After 40 min, they were subjected to the EPM test. In T2 (24 h later), each group was subdivided into two additional groups, and the animals from each group were re-injected with SAL or one of the drugs. In T1, the Student t-test showed no difference between the SAL and ZOL or 8 mg/kg CPA groups with respect to the percentages of open arm entries (%OAE) and open arm time (%OAT). However, administration of CPA at the highest dose of 16 mg/kg decreased %OAE and %OAT, but not locomotor activity, indicating anxiogenic-like behavior. Emotional memory, as revealed by a reduction in open arm exploration between the two trials, was observed in all experimental groups, indicating that ZOL and 8 mg/kg CPA did not affect emotional memory, whereas CPA at the highest dose affected acquisition and consolidation, but not retrieval of memory. Taken together, these results suggest that H1 receptor, but not H2, is implicated in anxiety-like behavior and in emotional memory acquisition and consolidation deficits in mice subjected to EPM testing.

Projeto e implementação em FPGA de um processador com conjunto de instrução reconfigurável utilizando VHDL

The Reconfigurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the flexibility of the software. An reconfigurable architecture possess some goals, among these the increase of performance. The use of reconfigurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use reconfigurable architectures the reconfigurable processors deserve a special mention. These processors combine the functions of a microprocessor with a reconfigurable logic and can be adapted after the development process. Reconfigurable Instruction Set Processors (RISP) are a subgroup of the reconfigurable processors, that have as goal the reconfiguration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of configuration of the set of executed instructions of the processor during the development, and reconfiguration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the efficiency of two concepts: to use more than one set of fixed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the fixed set of instruction. The creation and combination of instructions is made through a reconfiguration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were fixed instructions of the processor. In this work can also be found simulations of applications involving fixed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which confirm the attainment of the goals for which the processor was developed

Effects of isoflavone on the learning and memory of women in menopause: a double-blind placebo-controlled study

Hormone decline is common to all women during aging and, associated with other factors, leads to cognitive impairment. Its replacement enhances cognitive performance, but not all women present a clinical and family or personal history that justifies its use, mainly women with a history of cancer. The aim of this study was to determine whether a daily oral dose of 80 mg of isoflavone extract for 4 months can produce benefits in women with low hormone levels, contributing to improvement in cognitive aspects. The sample comprised 50- to 65-year-old women whose menstruation had ceased at least 1 year before and who had not undergone hormone replacement. The volunteers were allocated to two groups of 19 individuals each, i.e., isoflavone and placebo. There was a weak correlation between menopause duration and low performance in the capacity to manipulate information (central executive). We observed an increase in the capacity to integrate information in the group treated with isoflavone, but no improvement in the capacity to form new memories. We did not observe differences between groups in terms of signs and symptoms suggestive of depression according to the Geriatric Depression Scale. Our results point to a possible beneficial effect of isoflavone on some abilities of the central executive. These effects could also contribute to minimizing the impact of memory impairment. Further research based on controlled clinical trials is necessary to reach consistent conclusions.

LOSS of EXPONENTIAL STABILITY FOR A THERMOELASTIC SYSTEM WITH MEMORY

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)