Comunicação gráfica em interfaces de hipermídia de educação a distância via web

This study aims to analyze the communication graphics of layouts of hypermedia interfaces oriented to Distance Education via the Internet. This proposal is justified by widening the offer of courses that modality and the consequent application of items of hypermedia for teaching-learning. The method of analysis involved the search nethnographic, addressed to the cycle student intermediary of the Training Program Continuing Medias in Education, and the evaluation heuristic of the interfaces of Virtual Learning Environment "E-Proinfo" and of the modules of the Cycle. This evaluation we observed the implementation of the attributes of usability and the degree of interactivity of each interface. The results revealed an inefficient implementation of the attributes of usability, which meant a consequent reduction of the levels of interactivity. As proposing the present Design Virtual Learning, a model of hypermedia layout, designed to generate usability for Virtual learning environments and extend the acquisition of literancy for students and tutors. This proposal design not hypermedia aims the demarcation of models pre-conceived, but the proposal of layout in which each element of hypermedia is applied with a view to generate a seaworthiness intuitive, more agile and efficient, in these ambients

Infografia interativa na redação: o processo de produção no Diário do Nordeste à luz da teoria do jornalismo

The infographics historically experience the process of evolution of journalism, from the incipient models handmade in the eighteenth century to the inclusion of computers and sophisticated software today. In order to face the advent of TV against of the partiality readers of the printed newspaper, or to represent the Gulf War, where not allowed photography, infographics reaches modern levels of production and publication. The technical devices which enabled the infographics to evolve the environment of the internet, with conditions for the manipulation of the reader, incorporating video, audio and animations, so styling of interactive infographics. These digital models of information visualization recently arrived daily in the northeast and on their respective web sites with features regionalized. This paper therefore proposes to explore and describe the processes of producing the interactive infographics, taking the example of the Diário do Nordeste, Fortaleza, Ceará, whose department was created one year ago. Therefore, based on aspects that guide the theory of journalism, as newsmaking, filters that focus on productive routine (gatekeeping) and the construction stages of the news. This research also draws on the theoretical framework on the subject, in concepts essential characteristics of computer graphics, as well as the methodological procedures and systematic empirical observations in production routines of the newsroom who can testify limitations and / or advances

Generalization of the Y-differential autotransformer for 12- and 18-pulse converters

This work proposes a methodology to generalize the Y-connections for 12- and 18-pulse autotransformers. A single mathematical expression, obtained through simple trigonometric operations, represents all the connections. The proposed methodology allows choosing any ratio between the input and the output voltages. The converters can operate either as step-up or as step-down voltage. To simplify the design of the windings, graphics are generated to calculate the turn-ratio and the polarity of each secondary winding, with respect to the primary winding. A design example, followed by digital simulations, illustrates the presented steps. Experimental results of two prototypes (12 and 18 pulses) are presented. The results also show that high power factor is an inherent characteristic of multi-pulse converters, without any active or passive power factor pre-regulators needs. (c) 2005 Elsevier B.V. All rights reserved.

A novel HPF voltage source rectifier for variable speed refrigeration systems

A novel single-phase voltage source rectifier capable to achieve High-Power-Factor (HPF) for variable speed refrigeration system application, is proposed in this paper. The proposed system is composed by a single-phase high-power-factor boost rectifier, with two cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the EEC61000-3-2 standards. The digital controller for the output stage has been developed using a conventional voltage-frequency control (scalar V/f control), and a simplified stator oriented Vector control, in order to verify the feasibility and performance of the proposed digital controls for continuous temperature control applied at a refrigerator prototype.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests. (c) 2008 Elsevier B.V. All rights reserved.

An existence theorem for an analytic first order PDE in the framework of Colombeau's theory

We study the existence of a holomorphic generalized solution u of the PDE[GRAPHICS]where f is a given holomorphic generalized function and (alpha (1),...alpha (m)) is an element of C-m\{0}.

Avaliação da hipermídia no processo de ensino e aprendizagem da física: o caso da gravitação

Neste artigo são apresentados os principais resultados obtidos em uma atividade realizada para avaliar um software hipermídia destinado ao ensino e à aprendizagem da Física. Para a realização desta pesquisa, foi desenvolvido, aplicado e avaliado um sistema hipermídia para o ensino de Gravitação, com base nas pesquisas em ensino de Ciências. Foram considerados também os princípios fundamentais que caracterizam a hipermídia enquanto linguagem que permite o acesso não-linear à informação e a apresentação desta com a utilização dos recursos gráficos, sonoros, interativos e de animação do computador, e ainda suas implicações para as práticas de ensino. A maior parte dos professores e dos estudantes envolvidos na pesquisa avaliou positivamente o software quanto a seus aspectos técnicos, pedagógicos e motivacionais. O estudo forneceu evidências de que a hipermídia contribui para a aprendizagem de Física de modo motivador e significativo para os alunos do ensino médio.

Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys

The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform

Proposta e implementação de uma arquitetura reconfigurável híbrida para aplicações baseadas em fluxo de dados

The increase of applications complexity has demanded hardware even more flexible and able to achieve higher performance. Traditional hardware solutions have not been successful in providing these applications constraints. General purpose processors have inherent flexibility, since they perform several tasks, however, they can not reach high performance when compared to application-specific devices. Moreover, since application-specific devices perform only few tasks, they achieve high performance, although they have less flexibility. Reconfigurable architectures emerged as an alternative to traditional approaches and have become an area of rising interest over the last decades. The purpose of this new paradigm is to modify the device s behavior according to the application. Thus, it is possible to balance flexibility and performance and also to attend the applications constraints. This work presents the design and implementation of a coarse grained hybrid reconfigurable architecture to stream-based applications. The architecture, named RoSA, consists of a reconfigurable logic attached to a processor. Its goal is to exploit the instruction level parallelism from intensive data-flow applications to accelerate the application s execution on the reconfigurable logic. The instruction level parallelism extraction is done at compile time, thus, this work also presents an optimization phase to the RoSA architecture to be included in the GCC compiler. To design the architecture, this work also presents a methodology based on hardware reuse of datapaths, named RoSE. RoSE aims to visualize the reconfigurable units through reusability levels, which provides area saving and datapath simplification. The architecture presented was implemented in hardware description language (VHDL). It was validated through simulations and prototyping. To characterize performance analysis some benchmarks were used and they demonstrated a speedup of 11x on the execution of some applications

Utilizando mapas de conectividade fuzzy no desenvolvimento de algoritmos reparadores de imagens binárias 3D

A 3D binary image is considered well-composed if, and only if, the union of the faces shared by the foreground and background voxels of the image is a surface in R3. Wellcomposed images have some desirable topological properties, which allow us to simplify and optimize algorithms that are widely used in computer graphics, computer vision and image processing. These advantages have fostered the development of algorithms to repair bi-dimensional (2D) and three-dimensional (3D) images that are not well-composed. These algorithms are known as repairing algorithms. In this dissertation, we propose two repairing algorithms, one randomized and one deterministic. Both algorithms are capable of making topological repairs in 3D binary images, producing well-composed images similar to the original images. The key idea behind both algorithms is to iteratively change the assigned color of some points in the input image from 0 (background)to 1 (foreground) until the image becomes well-composed. The points whose colors are changed by the algorithms are chosen according to their values in the fuzzy connectivity map resulting from the image segmentation process. The use of the fuzzy connectivity map ensures that a subset of points chosen by the algorithm at any given iteration is the one with the least affinity with the background among all possible choices

Simulação de reservatórios de petróleo em ambiente MPSoC

The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit, the most viable solution is the use of parallelism. Based on parallelism techniques and the progressive growth in the capacity of transistors integration in a single chip is the concept of MPSoCs (Multi-Processor System-on-Chip). MPSoCs will eventually become a cheaper and faster alternative to supercomputers and clusters, and applications developed for these high performance systems will migrate to computers equipped with MP-SoCs containing dozens to hundreds of computation cores. In particular, applications in the area of oil and natural gas exploration are also characterized by the high processing capacity required and would benefit greatly from these high performance systems. This work intends to evaluate a traditional and complex application of the oil and gas industry known as reservoir simulation, developing a solution with integrated computational systems in a single chip, with hundreds of functional unities. For this, as the STORM (MPSoC Directory-Based Platform) platform already has a shared memory model, a new distributed memory model were developed. Also a message passing library has been developed folowing MPI standard

Projeto e implementação de uma plataforma MP-SoC usando SystemC

This work presents the concept, design and implementation of a MP-SoC platform, named STORM (MP-SoC DirecTory-Based PlatfORM). Currently the platform is composed of the following modules: SPARC V8 processor, GPOP processor, Cache module, Memory module, Directory module and two different modles of Network-on-Chip, NoCX4 and Obese Tree. All modules were implemented using SystemC, simulated and validated, individually or in group. The modules description is presented in details. For programming the platform in C it was implemented a SPARC assembler, fully compatible with gcc s generated assembly code. For the parallel programming it was implemented a library for mutex managing, using the due assembler s support. A total of 10 simulations of increasing complexity are presented for the validation of the presented concepts. The simulations include real parallel applications, such as matrix multiplication, Mergesort, KMP, Motion Estimation and DCT 2D

Paralelização em GPU da segmentação vascular com extração de Centerlines por Height Ridges

The vascular segmentation is important in diagnosing vascular diseases like stroke and is hampered by noise in the image and very thin vessels that can pass unnoticed. One way to accomplish the segmentation is extracting the centerline of the vessel with height ridges, which uses the intensity as features for segmentation. This process can take from seconds to minutes, depending on the current technology employed. In order to accelerate the segmentation method proposed by Aylward [Aylward & Bullitt 2002] we have adapted it to run in parallel using CUDA architecture. The performance of the segmentation method running on GPU is compared to both the same method running on CPU and the original Aylward s method running also in CPU. The improvemente of the new method over the original one is twofold: the starting point for the segmentation process is not a single point in the blood vessel but a volume, thereby making it easier for the user to segment a region of interest, and; the overall gain method was 873 times faster running on GPU and 150 times more fast running on the CPU than the original CPU in Aylward

Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios

The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with less heat dissipation, power consumption, and chip area. This goal has been achieved increasing the circuit clock, but since there are physical limits of this approach a new solution emerged as the multiprocessor system on chip (MPSoC). This approach demands new tools and basic software infrastructure to take advantage of the inherent parallelism of these architectures. The oil exploration industry has one of its firsts activities the project decision on exploring oil fields, those decisions are aided by reservoir simulations demanding high processing power, the MPSoC may offer greater performance if its parallelism can be well used. This work presents a proposal of a micro-kernel operating system and auxiliary libraries aimed to the STORM MPSoC platform analyzing its influence on the problem of reservoir simulation

RR3D: Uma solução para renderização remota de imagens médicas tridimensionais

The visualization of three-dimensional(3D)images is increasigly being sed in the area of medicine, helping physicians diagnose desease. the advances achived in scaners esed for acquisition of these 3d exames, such as computerized tumography(CT) and Magnetic Resonance imaging (MRI), enable the generation of images with higher resolutions, thus, generating files with much larger sizes. Currently, the images of computationally expensive one, and demanding the use of a righ and computer for such task. The direct remote acess of these images thruogh the internet is not efficient also, since all images have to be trasferred to the user´s equipment before the 3D visualization process ca start. with these problems in mind, this work proposes and analyses a solution for the remote redering of 3D medical images, called Remote Rendering (RR3D). In RR3D, the whole hedering process is pefomed a server or a cluster of servers, with high computational power, and only the resulting image is tranferred to the client, still allowing the client to peform operations such as rotations, zoom, etc. the solution was developed using web services written in java and an architecture that uses the scientific visualization packcage paraview, the framework paraviewWeb and the PACS server DCM4CHEE.The solution was tested with two scenarios where the rendering process was performed by a sever with graphics hadwere (GPU) and by a server without GPUs. In the scenarios without GPUs, the soluction was executed in parallel with several number of cores (processing units)dedicated to it. In order to compare our solution to order medical visualization application, a third scenario was esed in the rendering process, was done locally. In all tree scenarios, the solution was tested for different network speeds. The solution solved satisfactorily the problem with the delay in the transfer of the DICOM files, while alowing the use of low and computers as client for visualizing the exams even, tablets and smart phones