Arithmetic coding based lossless compression schemes for power system steady state operational data

Introduction of processor based instruments in power systems is resulting in the rapid growth of the measured data volume. The present practice in most of the utilities is to store only some of the important data in a retrievable fashion for a limited period. Subsequently even this data is either deleted or stored in some back up devices. The investigations presented here explore the application of lossless data compression techniques for the purpose of archiving all the operational data - so that they can be put to more effective use. Four arithmetic coding methods suitably modified for handling power system steady state operational data are proposed here. The performance of the proposed methods are evaluated using actual data pertaining to the Southern Regional Grid of India. (C) 2012 Elsevier Ltd. All rights reserved.

Power Controlled Reverse Channel Training Achieves an Infinite Diversity Order in a TDD-SIMO System with Perfect CSIR

In this letter, we analyze the Diversity Multiplexinggain Tradeoff (DMT) performance of a training-based reciprocal Single Input Multiple Output (SIMO) system. Assuming Channel State Information (CSI) is available at the Receiver (CSIR), we propose a channel-dependent power-controlled Reverse Channel Training (RCT) scheme that enables the transmitter to directly estimate the power control parameter to be used for the forwardlink data transmission. We show that, with an RCT power of (P) over bar (gamma), gamma > 0 and a forward data transmission power of (P) over bar, our proposed scheme achieves an infinite diversity order for 0 <= g(m) < L-c-L-B,L-tau/L-c min(gamma, 1) and r > 2, where g(m) is the multiplexing gain, L-c is the channel coherence time, L-B,L-tau is the RCT duration and r is the number of receive antennas. We also derive an upper bound on the outage probability and show that it goes to zero asymptotically as exp(-(P) over bar (E)), where E (sic) (gamma - g(m)L(c)/L-c-L-B,L-tau), at high (P) over bar. Thus, the proposed scheme achieves a significantly better DMT performance compared to the finite diversity order achieved by channel-agnostic, fixed-power RCT schemes.

Minimum power consumption for drag reduction on a circular cylinder by tangential surface motion

We investigate the effect of a prescribed tangential velocity on the drag force on a circular cylinder in a spanwise uniform cross flow. Using a combination of theoretical and numerical techniques we make an attempt at determining the optimal tangential velocity profiles which will reduce the drag force acting on the cylindrical body while minimizing the net power consumption characterized through a non-dimensional power loss coefficient (C-PL). A striking conclusion of our analysis is that the tangential velocity associated with the potential flow, which completely suppresses the drag force, is not optimal for both small and large, but finite Reynolds number. When inertial effects are negligible (R e << 1), theoretical analysis based on two-dimensional Oseen equations gives us the optimal tangential velocity profile which leads to energetically efficient drag reduction. Furthermore, in the limit of zero Reynolds number (Re -> 0), minimum power loss is achieved for a tangential velocity profile corresponding to a shear-free perfect slip boundary. At finite Re, results from numerical simulations indicate that perfect slip is not optimum and a further reduction in drag can be achieved for reduced power consumption. A gradual increase in the strength of a tangential velocity which involves only the first reflectionally symmetric mode leads to a monotonic reduction in drag and eventual thrust production. Simulations reveal the existence of an optimal strength for which the power consumption attains a minima. At a Reynolds number of 100, minimum value of the power loss coefficient (C-PL = 0.37) is obtained when the maximum in tangential surface velocity is about one and a half times the free stream uniform velocity corresponding to a percentage drag reduction of approximately 77 %; C-PL = 0.42 and 0.50 for perfect slip and potential flow cases, respectively. Our results suggest that potential flow tangential velocity enables energetically efficient propulsion at all Reynolds numbers but optimal drag reduction only for Re -> infinity. The two-dimensional strategy of reducing drag while minimizing net power consumption is shown to be effective in three dimensions via numerical simulation of flow past an infinite circular cylinder at a Reynolds number of 300. Finally a strategy of reducing drag, suitable for practical implementation and amenable to experimental testing, through piecewise constant tangential velocities distributed along the cylinder periphery is proposed and analysed.

Diversity-Rate Trade-off for Fading Channels with Power Control

We consider a complex, additive, white Gaussian noise channel with flat fading. We study its diversity order vs transmission rate for some known power allocation schemes. The capacity region is divided into three regions. For one power allocation scheme, the diversity order is exponential throughout the capacity region. For selective channel inversion (SCI) scheme, the diversity order is exponential in low and high rate region but polynomial in mid rate region. For fast fading case we also provide a new upper bound on block error probability and a power allocation scheme that minimizes it. The diversity order behaviour of this scheme is same as for SCI but provides lower BER than the other policies.

A multi-layer ultra wide band power splitter

This paper presents analysis and design of multilayer ultra wide band (UWB) power splitter suitable for wireless communications. An UWB power splitter is designed in suspended substrate stripline medium. The quarter wave transformer in the conventional Wilkinson power divider is replaced by broadside coupled lines to achieve tight coupling for broadband operation. The UWB power splitter is analyzed using circuit models of coupled lines and full wave simulator. Experimental results of 3dB power splitter designed using the proposed structure have been verified against the results from circuit simulation and full wave simulation. The return loss is better than 12 dB across the band 3.1GHz to 10.6GHz. Size of the power splitter is 30mm× 20mm×6.38mm.

Duty cycling and power management with a network of energy harvesting sensors

In this paper, we study duty cycling and power management in a network of energy harvesting sensor (EHS) nodes. We consider a one-hop network, where K EHS nodes send data to a destination over a wireless fading channel. The goal is to find the optimum duty cycling and power scheduling across the nodes that maximizes the average sum data rate, subject to energy neutrality at each node. We adopt a two-stage approach to simplify the problem. In the inner stage, we solve the problem of optimal duty cycling of the nodes, subject to the short-term power constraint set by the outer stage. The outer stage sets the short-term power constraints on the inner stage to maximize the long-term expected sum data rate, subject to long-term energy neutrality at each node. Albeit suboptimal, our solutions turn out to have a surprisingly simple form: the duty cycle allotted to each node by the inner stage is simply the fractional allotted power of that node relative to the total allotted power. The sum power allotted is a clipped version of the sum harvested power across all the nodes. The average sum throughput thus ultimately depends only on the sum harvested power and its statistics. We illustrate the performance improvement offered by the proposed solution compared to other naive schemes via Monte-Carlo simulations.

Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy

Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.

A constellation power allocation scheme for two-user Gaussian MAC

Constellation Constrained (CC) capacity regions of two-user Gaussian Multiple Access Channels (GMAC) have been recently reported, wherein introducing appropriate rotation between the constellations of the two users is shown to maximally enlarge the CC capacity region. Such a Non-Orthogonal Multiple Access (NO-MA) method of enlarging the CC capacity region is referred to as Constellation Rotation (CR) scheme. In this paper, we propose a novel NO-MA technique called Constellation Power Allocation (CPA) scheme to enlarge the CC capacity region of two-user GMAC. We show that the CPA scheme offers CC sum capacities equal (at low SNR values) or close (at high SNR values) to those offered by the CR scheme with reduced ML decoding complexity for some QAM constellations. For the CR scheme, code pairs approaching the CC sum capacity are known only for the class of PSK and PAM constellations but not for QAM constellations. In this paper, we design code pairs with the CPA scheme to approach the CC sum capacity for 16-QAM constellations. Further, the CPA scheme used for two-user GMAC with random phase offsets is shown to provide larger CC sum capacities at high SNR values compared to the CR scheme.

A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

Power scalable digital baseband architecture for IEEE 802.15.4

We propose a power scalable digital base band for a low-IF receiver for IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle worst case conditions. We propose tuning of these knobs based on measurements of Signal and the interference levels. We show that in a 0.13u CMOS technology, for an adaptive digital base band section of the receiver designed to meet the 802.15.4 standard specification, power saving can be up to nearly 85% (0.49mW against 3.3mW) in favorable interference and signal conditions.

Identification of coherent synchronous generators in a multi- machine power system using support vector clustering

This paper illustrates the application of a new technique, based on Support Vector Clustering (SVC) for the direct identification of coherent synchronous generators in a large interconnected Multi-Machine Power Systems. The clustering is based on coherency measures, obtained from the time domain responses of the generators following system disturbances. The proposed clustering algorithm could be integrated into a wide-area measurement system that enables fast identification of coherent clusters of generators for the construction of dynamic equivalent models. An application of the proposed method is demonstrated on a practical 15 generators 72-bus system, an equivalent of Indian Southern grid in an attempt to show the effectiveness of this clustering approach. The effects of short circuit fault locations on coherency are also investigated.

High power microwave coupling with a buried twisted pair cable

This paper deals with the coupling of High Power Microwaves with a buried twisted pair cable. The electric field at a distance of 1km from the HPM antenna has been computed and is used for further computation of induced voltage and current. It is found that the peak of the induced current and voltage in a buried unshielded twisted pair cable at a distance of 1km from an HPM antenna of power level 10GW is 20A and 2kV respectively.

A Novel Power Allocation Scheme for Two-User GMAC with Finite Input Constellations

Constellation Constrained (CC) capacity regions of two-user Gaussian Multiple Access Channels (GMAC) have been recently reported, wherein an appropriate angle of rotation between the constellations of the two users is shown to enlarge the CC capacity region. We refer to such a scheme as the Constellation Rotation (CR) scheme. In this paper, we propose a novel scheme called the Constellation Power Allocation (CPA) scheme, wherein the instantaneous transmit power of the two users are varied by maintaining their average power constraints. We show that the CPA scheme offers CC sum capacities equal (at low SNR values) or close (at high SNR values) to those offered by the CR scheme with reduced decoding complexity for QAM constellations. We study the robustness of the CPA scheme for random phase offsets in the channel and unequal average power constraints for the two users. With random phase offsets in the channel, we show that the CC sum capacity offered by the CPA scheme is more than the CR scheme at high SNR values. With unequal average power constraints, we show that the CPA scheme provides maximum gain when the power levels are close, and the advantage diminishes with the increase in the power difference.

Proportional resonant controller based circulating power setup for thermal testing of multilevel inverter

A regenerative or circulating-power method is presented in this paper for heat run test on the legs of a three-level neutral point clamped (NPC) inverter. This test ensures that only losses are drawn from the dc supply, while rated power is circulated between the two legs, thus minimising wastage of energy. A proportional-resonant (PR) controller based current control scheme is proposed here for the circulating power test setup in NPC inverter. Simulation and experimental results are presented to validate the controller design at various operating conditions. Results of thermal test on the inverter legs are presented at two different operating conditions.

Circulating power test setup for a PWM rectifier motor drive

Power converters burn-in test consumes large amount of energy, which increases the cost of testing, and certification, in medium and high power application. A simple test configuration to test a PWM rectifier induction motor drive, using a Doubly Fed Induction Machine (DFIM) to circulate power back to the grid for burn-in test is presented. The test configuration makes use of only one power electronic converter, which is the converter to be tested. The test method ensures soft synchronization of DFIM and Squirrel Cage Induction Machine (SCIM). A simple volt per hertz control of the drive is sufficient for conducting the test. To synchronize the DFIM with SCIM, the rotor terminal voltage of DFIM is measured and used as an indication of speed mismatch between DFIM and SCIM. The synchronization is done when the DFIM rotor voltage is at its minimum. Analysis of the DFIM characteristics confirms that such a test can be effectively performed with smooth start up and loading of the test setup. After synchronization is obtained, the speed command to SCIM is changed in order to load the setup in motoring or regenerative mode of operation. The experimental results are presented that validates the proposed test method.