Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Performance analysis for geometrical attack on digital image watermarking

We present a technique for irreversible watermarking approach robust to affine transform attacks in camera, biomedical and satellite images stored in the form of monochrome bitmap images. The watermarking approach is based on image normalisation in which both watermark embedding and extraction are carried out with respect to an image normalised to meet a set of predefined moment criteria. The normalisation procedure is invariant to affine transform attacks. The result of watermarking scheme is suitable for public watermarking applications, where the original image is not available for watermark extraction. Here, direct-sequence code division multiple access approach is used to embed multibit text information in DCT and DWT transform domains. The proposed watermarking schemes are robust against various types of attacks such as Gaussian noise, shearing, scaling, rotation, flipping, affine transform, signal processing and JPEG compression. Performance analysis results are measured using image processing metrics.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Digital Simulation of Field-Oriented Control of Induction Motor

This paper describes the simulation of a control scheme using the principle of field orientation for the control of a voltage source inverter-fed induction motor. The control principle is explained, followed by an algorithm to simulate various components of the system in the digital computer. The dynamic response of the system for the load disturbance and set-point variations have been studied. Also, the results of the simulation showing the behavior of field coordinates for such disturbances are given.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Automatic Recognition of Facial Features and Landmarking of Digital Human Head

Ergonomic design of products demands accurate human dimensions-anthropometric data. Manual measurement over live subjects, has several limitations like long time, required presence of subjects for every new measurement, physical contact etc. Hence the data currently available is limited and anthropometric data related to facial features is difficult to obtain. In this paper, we discuss a methodology to automatically detect facial features and landmarks from scanned human head models. Segmentation of face into meaningful patches corresponding to facial features is achieved by Watershed algorithms and Mathematical Morphology tools. Many Important physiognomical landmarks are identified heuristically.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Surface electrode switching of a 16-electrode wireless EIT system using RF-based digital data transmission scheme with 8 channel encoder/decoder ICs

A Radio Frequency (RF) based digital data transmission scheme with 8 channel encoder/decoder ICs is proposed for surface electrode switching of a 16-electrode wireless Electrical Impedance Tomography (EIT) system. A RF based wireless digital data transmission module (WDDTM) is developed and the electrode switching of a EIT system is studied by analyzing the boundary data collected and the resistivity images of practical phantoms. An analog multiplexers based electrode switching module (ESM) is developed with analog multiplexers and switched with parallel digital data transmitted by a wireless transmitter/receiver (T-x/R-x) module working with radio frequency technology. Parallel digital bits are generated using NI USB 6251 card working in LabVIEW platform and sent to transmission module to transmit the digital data to the receiver end. The transmitter/receiver module developed is properly interfaced with the personal computer (PC) and practical phantoms through the ESM and USB based DAQ system respectively. It is observed that the digital bits required for multiplexer operation are sequentially generated by the digital output (D/O) ports of the DAQ card. Parallel to serial and serial to parallel conversion of digital data are suitably done by encoder and decoder ICs. Wireless digital data transmission module successfully transmitted and received the parallel data required for switching the current and voltage electrodes wirelessly. 1 mA, 50 kHz sinusoidal constant current is injected at the phantom boundary using common ground current injection protocol and the boundary potentials developed at the voltage electrodes are measured. Resistivity images of the practical phantoms are reconstructed from boundary data using EIDORS. Boundary data and the resistivity images reconstructed from the surface potentials are studied to assess the wireless digital data transmission system. Boundary data profiles of the practical phantom with different configurations show that the multiplexers are operating in the required sequence for common ground current injection protocol. The voltage peaks obtained at the proper positions in the boundary data profiles proved the sequential operation of multiplexers and successful wireless transmission of digital bits. Reconstructed images and their image parameters proved that the boundary data are successfully acquired by the DAQ system which in turn again indicates a sequential and proper operation of multiplexers as well as the successful wireless transmission of digital bits. Hence the developed RF based wireless digital data transmission module (WDDTM) is found suitable for transmitting digital bits required for electrode switching in wireless EIT data acquisition system. (C) 2011 Elsevier Ltd. All rights reserved.

High resolution facies record on late Holocene flood plain sediments from lower reaches of Narmada Valley, Western India

A high resolution quantitative granulometric record for site Uchediya 21A degrees 43'2.22aEuro(3) N, 73A degrees 6'26.22aEuro(3) E; 10 m a. s. l.] gives understanding towards accretion history of the late Holocene flood plain in the lower reaches of Narmada River. Two sediment facies (sandy and muddy) and seven subfacies (sandy subfacies: St(MS+FS+CS), SmFS+MS, Sl(FS+VFS), and St(MS + CS); muddy subfacies: FmSILT+VFS+FS, FmSILT+VFS (O) and FmSILT+VFS (T)) are identified based on cluster analysis supplemented with sedimentary structures observed in field and other laboratory data. Changes in hydrodynamics are further deduced based on various sedimentological parameters and their ratios leading to arrive at a depositional model.

A digital herbarium for the flora of Karnataka

A herbarium-based database (virtual herbarium) is a referral system for plants that maximizes the usefulness of the collections. The information content of such a database is essentially built on the voucher specimens that the herbarium has in its care. The present article reports on the construction of a `virtual herbarium' for the state-wide collection of flowering plants in the Herbarium JCB housed at the Centre for Ecological Sciences, Indian Institute of Science, Bangalore, that is expected to be launched soon. The taxonomic data on each species include all information presented on the herbarium specimen label, namely species name, author citation, sub-species if any, variety if any, family, subfamily, collection number, locations, date of collection, habitat and the collector's name. The data further comprise `flora' in which the species are described. Additional information includes the nomenclature update according to `The Plant List', a detailed description, phenology, species distribution, threat status and comments on any special features of the taxon. The live images of the species provided in the database form an information synergy on the species. This initiative is the first of its kind for herbaria in peninsular India.

Climatic fluctuations during the LIA and post-LIA in the Kumaun Lesser Himalaya, India: Evidence from a 400 y old stalagmite record

This paper presents the first stable isotope (delta O-18 and delta C-13) data of a similar to 400 years (1590-2006 AD) long annual to decadal-resolution speleothem record collected from the Indian Lesser Himalaya. The data show a variation from -2.7 to -5.9 parts per thousand in delta O-18 and -5.3 to -8.8 parts per thousand in delta C-13. The isotopic analyses indicate that the climate during this period can be divided into two stages: a wet phase during the Little Ice Age (LIA) (1590-1850 AD) and comparatively dry phase during the post-LIA after 1850 AD. However, the record also documents the minor dry events during the LIA and a wet episode after the LIA. Within the age uncertainty, the dry spells during the LIA are linked with the historical drought events in the Indian subcontinent and similar latitudes. The isotopic record is consistent with a number of previous studies in the areas influenced by the Westerlies but appears to be conflicting to the regions, dominated by the Indian Summer Monsoon (ISM). This may be due to the possible changes in the strength of Westerlies in the study area and added by negative anomaly of North Atlantic Oscillation (NAO) during the LIA. (C) 2012 Elsevier Ltd and INQUA. All rights reserved.

Switching of a Sixteen Electrode Array for Wireless EIT System Using a RF-Based 8-Bit Digital Data Transmission Technique

Surface electrode switching of 16-electrode wireless EIT is studied using a Radio Frequency (RF) based digital data transmission technique operating with 8 channel encoder/decoder ICs. An electrode switching module is developed the analog multiplexers and switched with 8-bit parallel digital data transferred by transmitter/receiver module developed with radio frequency technology. 8-bit parallel digital data collected from the receiver module are converted to 16-bit digital data by using binary adder circuits and then used for switching the electrodes in opposite current injection protocol. 8-bit parallel digital data are generated using NI USB 6251 DAQ card in LabVIEW software and sent to the transmission module which transmits the digital data bits to the receiver end. Receiver module supplies the parallel digital bits to the binary adder circuits and adder circuit outputs are fed to the multiplexers of the electrode switching module for surface electrode switching. 1 mA, 50 kHz sinusoidal constant current is injected at the phantom boundary using opposite current injection protocol. The boundary potentials developed at the voltage electrodes are measured and studied to assess the wireless data transmission.

Power scalable digital baseband architecture for IEEE 802.15.4

We propose a power scalable digital base band for a low-IF receiver for IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle worst case conditions. We propose tuning of these knobs based on measurements of Signal and the interference levels. We show that in a 0.13u CMOS technology, for an adaptive digital base band section of the receiver designed to meet the 802.15.4 standard specification, power saving can be up to nearly 85% (0.49mW against 3.3mW) in favorable interference and signal conditions.