Significance Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator

In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scalable, process variation aware motion estimator based on significance driven computation. The fundamental premise of our approach lies in the fact that all computations are not equally significant in shaping the output response of video systems. We use a statistical technique to intelligently identify these significant/not-so-significant computations at the algorithmic level and subsequently change the underlying architecture such that the significant computations are computed in an error free manner under voltage over-scaling. Furthermore, our design includes an adaptive quality compensation (AQC) block which "tunes" the algorithm and architecture depending on the magnitude of voltage over-scaling and severity of process variations. Simulation results show average power savings of similar to 33% for the proposed architecture when compared to conventional implementation in the 90 nm CMOS technology. The maximum output quality loss in terms of Peak Signal to Noise Ratio (PSNR) was similar to 1 dB without incurring any throughput penalty.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

New modular structure DC-DC converter without electrolytic capacitors for renewable energy applications

Fair charging strategies for EVs connected to a low-voltage distribution network

The development of smart grid technologies and appropriate charging strategies are key to accommodating large numbers of Electric Vehicles (EV) charging on the grid. In this paper a general framework is presented for formulating the EV charging optimization problem and three different charging strategies are investigated and compared from the perspective of charging fairness while taking into account power system constraints. Two strategies are based on distributed algorithms, namely, Additive Increase and Multiplicative Decrease (AIMD), and Distributed Price-Feedback (DPF), while the third is an ideal centralized solution used to benchmark performance. The algorithms are evaluated using a simulation of a typical residential low voltage distribution network with 50% EV penetration. © 2013 IEEE.

Investigation of AIMD based charging strategies for EVs connected to a low-voltage distribution network

In this paper we consider charging strategies that mitigate the impact of domestic charging of EVs on low-voltage distribution networks and which seek to reduce peak power by responding to time-ofday pricing. The strategies are based on the distributed Additive Increase and Multiplicative Decrease (AIMD) charging algorithms proposed in [5]. The strategies are evaluated using simulations conducted on a custom OpenDSS-Matlab platform for a typical low voltage residential feeder network. Results show that by using AIMD based smart charging 50% EV penetration can be accommodated on our test network, compared to only 10% with uncontrolled charging, without needing to reinforce existing network infrastructure. © Springer-Verlag Berlin Heidelberg 2013.

On-off based charging strategies for EVs connected to a Low Voltage distributon network

The development of appropriate Electric Vehicle (EV) charging strategies has been identified as an effective way to accommodate an increasing number of EVs on Low Voltage (LV) distribution networks. Most research studies to date assume that future charging facilities will be capable of regulating charge rates continuously, while very few papers consider the more realistic situation of EV chargers that support only on-off charging functionality. In this work, a distributed charging algorithm applicable to on-off based charging systems is presented. Then, a modified version of the algorithm is proposed to incorporate real power system constraints. Both algorithms are compared with uncontrolled and centralized charging strategies from the perspective of both utilities and customers. © 2013 IEEE.

Azepanium-based ionic liquids as green electrolytes for high voltage supercapacitors

This work provides a first-time-study of Azepanium-based ionic liquids (ILs) as electrolyte components for electrochemical double layer capacitors (EDLCs). Herein, two Azepanium-based ILs, namely N-methyl, N-butyl-azepanium bis(trifluoromethanesulfonyl)imide (Azp(14)TFSI) and N-methyl, N-hexyl-azepanium bis(trifluoromethanesulfonyl)imide (Azp(16)TFSI) were compared with the established IL N-butyl, N-methylpyrrolidinium bis(trifluoromethanesulfonyl)imide (Pyr(14)TFSI) in terms of viscosity, conductivity, thermal stability and electrochemical behavior in EDLC systems. The ILs' operative potentials were found to be comparable, leading to operative voltages up to 3.5 V without significant electrolyte degradation. 

Mixtures of azepanium based ionic liquids and propylene carbonate as high voltage electrolytes for supercapacitors

This work provides a study of mixtures of the azepanium-based ionic liquid (IL) N-methyl, N-butyl-azepanium bis[(trifluoromethane) sulfonyl]imide (Azp₁₄TFSI) and propylene carbonate (PC) as electrolyte components in electrochemical double layer capacitors (EDLCs). The considered mixtures' properties were then compared to the properties of mixtures of N-butyl, N-methylpyrrolidinium bis[(trifluoromethane) sulfonyl]imide (Pyr₁₄TFSI) and PC in terms of viscosity, conductivity and electrochemical behavior. The mixtures' operative potentials were found to be comparable to each other, leading to operative voltages as high as 3.5 V, while retaining the low viscosities and high conductivities of PC based EDLC electrolytes.

Droop setting design for multi-terminal HVDC grids considering voltage deviation impacts

In multi-terminal high voltage direct current (HVDC) grids, the widely deployed droop control strategies will cause a non-uniform voltage deviation on the power flow, which is determined by the network topology and droop settings. This voltage deviation results in an inconsistent power flow pattern when the dispatch references are changed, which could be detrimental to the operation and seamless integration of HVDC grids. In this paper, a novel droop setting design method is proposed to address this problem for a more precise power dispatch. The effects of voltage deviations on the power sharing accuracy and transmission loss are analysed. This paper shows that there is a trade-off between minimizing the voltage deviation, ensuring a proper power delivery and reducing the total transmission loss in the droop setting design. The efficacy of the proposed method is confirmed by simulation studies.

Adaptive backstepping droop controller design for multi-terminal high-voltage direct current systems

Wind power is one of the most developed renewable energy resources worldwide. To integrate offshore wind farms to onshore grids, the high-voltage direct current (HVDC) transmission cables interfaced with voltage source converters (VSCs) are considered to be a better solution than conventional approaches. Proper DC voltage indicates successive power transfer. To connect more than one onshore grid, the DC voltage droop control is one of the most popular methods to share the control burden between different terminals. However, the challenges are that small droop gains will cause voltage deviations, while higher droop gain settings will cause large oscillations. This study aims to enhance the performance of the traditional droop controller by considering the DC cable dynamics. Based on the backstepping control concept, DC cables are modelled with a series of capacitors and inductors. The final droop control law is deduced step-by-step from the original remote side. At each step the control error from the previous step is considered. Simulation results show that both the voltage deviations and oscillations can be effectively reduced using the proposed method. Further, power sharing between different terminals can be effectively simplified such that it correlates linearly with the droop gains, thus enabling simple yet accurate system operation and control.

CaV3.1 T-Type Ca2+ Channels Contribute to Myogenic Signalling in Rat Retinal Arterioles

Purpose: Although L-type Ca2+ channels are known to play a key role in the myogenic reactivity of retinal arterial vessels, the involvement of other types of voltage-gated Ca2+ channels in this process remains unknown. In the present study we have investigated the contribution of T-type Ca2+ channels to myogenic signalling in arterioles of the rat retinal microcirculation.

Methods: Confocal immunolabelling of wholemount preparations was used to investigate the localisation of CaV3.1-3 channels in retinal arteriolar smooth muscle cells. T-type currents and the contribution of T-type channels to myogenic signalling were assessed by whole-cell patch-clamp recording and pressure myography of isolated retinal arteriole segments.

Results: Strong immunolabelling for CaV3.1 was observed on the plasma membrane of retinal arteriolar smooth muscle cells. In contrast, no expression of CaV3.2 or CaV3.3 could be detected in retinal arterioles, although these channels were present on glial cell end feet surrounding the vessels and retinal ganglion cells, respectively. TTA-A2 sensitive T-type currents were recorded in retinal arteriolar myocytes with biophysical properties distinct from those of the L-type currents present in these cells. Inhibition of T-type channels using TTA-A2 or ML-218 dilated isolated, myogenically active, retinal arterioles.

Conclusions: CaV3.1 T-type Ca2+ channels are functionally expressed on arteriolar smooth muscle cells of retinal arterioles and play an important role in myogenic signalling in these vessels. The work has important implications concerning our understanding of the mechanisms controlling blood flow autoregulation in the retina and its disruption during ocular disease.

An approach to determine the local boundary of small disturbance voltage stability region in a cut-set power space:基于微扰的割集电压稳定域局部边界求解方法

A new approach to determine the local boundary of voltage stability region in a cut-set power space (CVSR) is presented. Power flow tracing is first used to determine the generator-load pair most sensitive to each branch in the interface. The generator-load pairs are then used to realize accurate small disturbances by controlling the branch power flow in increasing and decreasing directions to obtain new equilibrium points around the initial equilibrium point. And, continuous power flow is used starting from such new points to get the corresponding critical points around the initial critical point on the CVSR boundary. Then a hyperplane cross the initial critical point can be calculated by solving a set of linear algebraic equations. Finally, the presented method is validated by some systems, including New England 39-bus system, IEEE 118-bus system, and EPRI-1000 bus system. It can be revealed that the method is computationally more efficient and has less approximation error. It provides a useful approach for power system online voltage stability monitoring and assessment. This work is supported by National Natural Science Foundation of China (No. 50707019), Special Fund of the National Basic Research Program of China (No. 2009CB219701), Foundation for the Author of National Excellent Doctoral Dissertation of PR China (No. 200439), Tianjin Municipal Science and Technology Development Program (No. 09JCZDJC25000), National Major Project of Scientific and Technical Supporting Programs of China During the 11th Five-year Plan Period (No. 2006BAJ03A06). ©2009 State Grid Electric Power Research Institute Press.