On the potential of significance-driven execution for energy-aware HPC

Dynamic Voltage and Frequency Scaling (DVFS) exhibits fundamental limitations as a method to reduce energy consumption in computing systems. In the HPC domain, where performance is of highest priority and codes are heavily optimized to minimize idle time, DVFS has limited opportunity to achieve substantial energy savings. This paper explores if operating processors Near the transistor Threshold Volt- age (NTV) is a better alternative to DVFS for break- ing the power wall in HPC. NTV presents challenges, since it compromises both performance and reliability to reduce power consumption. We present a first of its kind study of a significance-driven execution paradigm that selectively uses NTV and algorithmic error tolerance to reduce energy consumption in performance- constrained HPC environments. Using an iterative algorithm as a use case, we present an adaptive execution scheme that switches between near-threshold execution on many cores and above-threshold execution on one core, as the computational significance of iterations in the algorithm evolves over time. Using this scheme on state-of-the-art hardware, we demonstrate energy savings ranging between 35% to 67%, while compromising neither correctness nor performance.

The development of internal water cooling techniques for the rotational moulding process

This paper reports the findings from internal mould cooling trials using a water spray configuration applied at various internal mould air temperatures from 120°C to 180°C for an aluminium mould. To achieve maximum benefit in terms of cycle time reduction, internal mould water cooling was used in conjunction with a combination of external forced air and water cooling. Savings in cooling times of up to 30% were achieved compared to conventional external only forced air cooling.

Energy Efficiency through Significance-Based Computing

An extension of approximate computing, significance-based computing exploits applications' inherent error resiliency and offers a new structural paradigm that strategically relaxes full computational precision to provide significant energy savings with minimal performance degradation.

Factors Influencing the Implementation of Site Waste Management Plans on UK Projects of all sizes

The purpose of this research is to identify and assess the opportunities and challenges of implementing a Site Waste Management Plan (SWMP) on projects irrespective of size. In the UK, construction and demolition waste accounts for a third of all UK waste. There are a number of factors that influence the implementation of SWMPs. In order to identify and analyse these factors, 4 unstructured interviews were carried out and a sample of 56 participants completed a questionnaire survey. The scope of the study was limited to UK<br/>construction industry professionals. The analysis revealed that more needs to be done if the industry is to meet government targets of reduction in construction related waste going to landfill. In addition, although SWMP may not yet be legally required on all construction projects, clients and contractors need to realise<br/>the benefits to cut costs and implement best practice by adopting a SWMP. The benefits of implementing a SWMP will not only help to achieve this but also gain significant cost savings on projects and is also extremely beneficial to the environment. This study presents evidence that contractors need to do more to reduce waste and draws a clear link between waste reduction and the implementation of SWMPs. The findings are useful in the ongoing efforts to encourage the industry to find smarter, more efficient and less<br/>damaging ways to operate

Material Logistics in Urban Construction Sites: A Structural Equation Model

Aim: The aim of this paper is to identify best practice relating to the effective management of materials in an urban, confined construction site, using structural equation modelling.<br/><br/>Methodology: A literature review, case study analysis and questionnaire survey are employed, with the results scrutinised using confirmatory factor analysis in the form of structural equation modelling.<br/><br/>Results: The following are the leading strategies in the management of materials in a confined urban site environment; (1) Consult and review the project programme, (2) Effective communication and delivery, (3) Implement site safety management plans, and (4) Proactive spatial monitoring and control.<br/><br/>Implication for Practice: With the relentless expansion of urban centres and the increasing high cost of materials, any potential savings made on-site would translate into significant monetary concessions on completion of a development.<br/><br/>Originality/Value: As on-site project management professionals successfully identify and implement the various strategies in the management of plant and materials on a confined urban site, successful resource management in this restrictive environment is attainable.<br/><br/>Innovative Aspect of Paper: An empirical study of three different construction sites in three different countries (Ireland, England and USA) together with a questionnaire survey from the industry, investigating the managerial strategies in the management of plant and material in confined urban site environments<br/>

Shared Services in Ireland

The global financial crisis has forced governments across the globe to seek new ways of achieving efficiencies and savings in running their state administrations. Prominent amongst the variety of approaches adopted is the concept of shared services, which purports to offer a means of consolidating common tasks, reducing duplication, and achieving greater value for money. Based on successful experiences in the private sector, the phenomenon of shared service centres (SSCs) as a new co-ordination practice is of particular interest. In this chapter, the use of shared services and SSCs in Ireland is considered.

Bicameralism in the Republic of Ireland: The Seanad Abolition Referendum

Whether or not a legislature is uni- or bi-cameral has been found to have important consequences. Ireland's 1937 constitution provided for a directly elected lower chamber (Dáil Éireann) and an indirectly elected upper chamber (Seanad Éireann). With the appointment to government in 2011 of two political parties with a common electoral commitment to abolish bicameralism, the subsequent coalition agreement included a promise to hold a referendum offering voters the option to move to a unicameral parliamentary system. On 4 October 2013, the electorate voted to retain the upper chamber, albeit by a narrow majority of 51.7 per cent, on a turnout of 39.17 per cent. The outcome was arguably surprising, given that opinion polls signalled a plurality of voters favoured abolition, and there was a general public antipathy towards political institutions in the midst of a major economic crisis. Public opinion research suggests that a combination of factors explained voting behaviour, including a lack of interest amongst those who did not vote. A cost savings argument was a significant factor for those favouring abolition, while concerns over government control of the legislative process appear to have been most prominent in the minds of those who voted to retain the upper chamber.

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

In this paper, we have developed a low-complexity algorithm for epileptic seizure detection with a high degree of accuracy. The algorithm has been designed to be feasibly implementable as battery-powered low-power implantable epileptic seizure detection system or epilepsy prosthesis. This is achieved by utilizing design optimization techniques at different levels of abstraction. Particularly, user-specific critical parameters are identified at the algorithmic level and are explicitly used along with multiplier-less implementations at the architecture level. The system has been tested on neural data obtained from in-vivo animal recordings and has been implemented in 90nm bulk-Si technology. The results show up to 90 % savings in power as compared to prevalent wavelet based seizure detection technique while achieving 97% average detection rate. Copyright 2010 ACM.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

HERQULES:System level cross-layer design exploration for efficient energy-quality trade-offs

In this paper, we present a unique cross-layer design framework that allows systematic exploration of the energy-delay-quality trade-offs at the algorithm, architecture and circuit level of design abstraction for each block of a system. In addition, taking into consideration the interactions between different sub-blocks of a system, it identifies the design solutions that can ensure the least energy at the "right amount of quality" for each sub-block/system under user quality/delay constraints. This is achieved by deriving sensitivity based design criteria, the balancing of which form the quantitative relations that can be used early in the system design process to evaluate the energy efficiency of various design options. The proposed framework when applied to the exploration of energy-quality design space of the main blocks of a digital camera and a wireless receiver, achieves 58% and 33% energy savings under 41% and 20% error increase, respectively. © 2010 ACM.

VEDA:Variation-aware energy-efficient discrete Wavelet Transform architecture

In this paper, we present a unified approach to an energy-efficient variation-tolerant design of Discrete Wavelet Transform (DWT) in the context of image processing applications. It is to be noted that it is not necessary to produce exactly correct numerical outputs in most image processing applications. We exploit this important feature and propose a design methodology for DWT which shows energy quality tradeoffs at each level of design hierarchy starting from the algorithm level down to the architecture and circuit levels by taking advantage of the limited perceptual ability of the Human Visual System. A unique feature of this design methodology is that it guarantees robustness under process variability and facilitates aggressive voltage over-scaling. Simulation results show significant energy savings (74% - 83%) with minor degradations in output image quality and avert catastrophic failures under process variations compared to a conventional design. © 2010 IEEE.

Process variation tolerant low power DCT architecture

<p>2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) &gt; 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.</p>

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

<p>Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.</p>