Ultra-low conductivity noise in metallic nanowires

By modifying the electrodeposition technique, we have stabilized the silver nanowires (AgNWs) in high-energy hexagonal closed packed (hcp)structure. The conductivity noise measurements show that the noise magnitude in hcp silver nanowires is several orders of magnitude smaller than that of face centered cubic (fcc) silver nanowires, which is obtained by standard over potential lectrodeposition (OPD)technique. The reduction of noise can be attributed to the restricted dislocation dynamics in hcp AgNWs due to the presence of less number of slip systems. Temperature dependent noise measurements show that the noise magnitude in hcp AgNWs is weakly temperature dependent while in fcc AgNWs it is strong function of temperature.

A new family of low-power CT/SUP 2/L circuits

A new family of low-power logic circuits, employing a multiemitter transistor input circuit and a modified complementary p-n-p n-p-n output stage, having almost the same performance as standard TTL circuits and suitable for IC use, is reported in this correspondence.

Low power pipelined TCAM employing mismatch dependent power allocation technique

This paper presents design of a Low power 256x72 bit TCAM in 0.13um CMOS technology. In contrast to conventional Match line (ML) sensing scheme in which equal power is consumed irrespective of match or mismatch, the ML scheme employed in this design allocates less power to match decisions involving a large number of mismatched bits. Typically, the probability of mismatch is high so this scheme results in significant CAM power reduction. We propose to use this technique along with pipelining of search operation in which the MLs are broken into several segments. Since most words fail to match in first segment, the search operation for subsequent segments is discontinued, resulting in further reduction in power consumption. The above architecture provides 70% power reduction while performing search in 3ns.

Photobiomodulation by Low Power Laser Irradiation Involves Activation of Latent TGF-β1

Laser mediated stimulation of biological process was amongst its very first effects documented by Mester et al. but the ambiguous and tissue-cell context specific biological effects of laser radiation is now termed ‘Photobiomodulation’. We found many parallels between the reported biological effects of lasers and a multiface-ted growth factor, Transforming Growth Factor-β (TGF-β). This review outlines the interestingparallelsbetween the twofieldsand our rationalefor pursuingtheir potential causal correlation. We explored this correlation using an in vitro assay systems and a human clinical trial on healing wound extraction sockets that we reported in a recent publication. In conclusion we report that low power laser irradiation can activate latent TGF-β1 and β3 complexes and suggest that this might be one of the major modes of the photobiomodulatory effects of low power lasers.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Studies on age-hardening characteristics of ceramic particle/matrix interfaces in Al-Cu-SiCp composites using ultra low-load-dynamic microhardness measurements

Ultra low-load-dynamic microhardness testing facilitates the hardness measurements in a very low volume of the material and thus is suited for characterization of the interfaces in MMC's. This paper details the studies on age-hardening behavior of the interfaces in Al-Cu-5SiC(p) composites characterized using this technique. Results of hardness studies have been further substantiated by TEM observations. In the solution-treated condition, hardness is maximum at the particle/matrix interface and decreases with increasing distance from the interface. This could be attributed to the presence of maximum dislocation density at the interface which decreases with increasing distance from the interface. In the case of composites subjected to high temperature aging, hardening at the interface is found to be faster than the bulk matrix and the aging kinetics becomes progressively slower with increasing distance from the interface. This is attributed to the dislocation density gradient at the interface, leading to enhanced nucleation and growth of precipitates at the interface compared to the bulk matrix. TEM observations reveal that the sizes of the precipitates decrease with increasing distance from the interface and thus confirms the retardation in aging kinetics with increasing distance from the interface.

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.

Starting scheme for load commutated inverter-fed wound field synchronous machine using an auxiliary low-power voltage source inverter

Conventional thyristor-based load commutated inverter (LCI)-fed wound field synchronous machine operates only above a minimum speed that is necessary to develop enough back emf to ensure commutation. The drive is started and brought up to a speed of around 10-15% by a complex `dc link current pulsing' technique. During this process, the drive have problems such as pulsating torque, insufficient average starting torque, longer starting time, etc. In this regard a simple starting and low-speed operation scheme, by employing an auxiliary low-power voltage source inverter (VSI) between the LCI and the machine terminals, is presented in this study. The drive is started and brought up to a low speed of around 15% using the VSI alone with field oriented control. The complete control is then smoothly and dynamically transferred to the conventional LCI control. After the control transfer, the VSI is turned off and physically disconnected from the main circuit. The advantages of this scheme are smooth starting, complete control of torque and flux at starting and low speeds, less starting time, stable operation, etc. The voltage rating of the required VSI is very low of the order of 10-15%, whereas the current rating is dependent on the starting torque requirement of the load. The experimental results from a 15.8 hp LCI-fed wound field synchronous machine are given to demonstrate the scheme.

Optimal Power and Noise for Analog and Digital Sections of a Low Power Radio Receiver

We determine the optimal allocation of power between the analog and digital sections of an RF receiver while meeting the BER constraint. Unlike conventional RF receiver designs, we treat the SNR at the output of the analog front end (SNRAD) as a design parameter rather than a specification to arrive at this optimal allocation. We first determine the relationship of the SNRAD to the resolution and operating frequency of the digital section. We then use power models for the analog and digital sections to solve the power minimization problem. As an example, we consider a 802.15.4 compliant low-IF receiver operating at 2.4 GHz in 0.13 μm technology with 1.2 V power supply. We find that the overall receiver power is minimized by having the analog front end provide an SNR of 1.3dB and the ADC and the digital section operate at 1-bit resolution with 18MHz sampling frequency while achieving a power dissipation of 7mW.

An Adaptive Feature Based Low Power Motion Estimation Algorithm

Motion Estimation is one of the most power hungry operations in video coding. While optimal search (eg. full search)methods give best quality, non optimal methods are often used in order to reduce cost and power. Various algorithms have been used in practice that trade off quality vs. complexity. Global elimination is an algorithm based on pixel averaging to reduce complexity of motion search while keeping performance close to that of full search. We propose an adaptive version of the global elimination algorithm that extracts individual macro-block features using Hadamard transform to optimize the search. Performance achieved is close to the full search method and global elimination. Operational complexity and hence power is reduced by 30% to 45% compared to global elimination method.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Reduced Rate Ultra Low Delay Audio Coder using Multistage Vector Quantization

Communication applications are usually delay restricted, especially for the instance of musicians playing over the Internet. This requires a one-way delay of maximum 25 msec and also a high audio quality is desired at feasible bit rates. The ultra low delay (ULD) audio coding structure is well suited to this application and we investigate further the application of multistage vector quantization (MSVQ) to reach a bit rate range below 64 Kb/s, in a scalable manner. Results at 32 Kb/s and 64 Kb/s show that the trained codebook MSVQ performs best, better than KLT normalization followed by a simulated Gaussian MSVQ or simulated Gaussian MSVQ alone. The results also show that there is only a weak dependence on the training data, and that we indeed converge to the perceptual quality of our previous ULD coder at 64 Kb/s.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.