A Reduced Device-Count Hybrid Multilevel Inverter Topology with single DC Source and Improved Fault Tolerance

A new hybrid multilevel power converter topology is presented in this paper. The proposed power converter topology uses only one DC source and floating capacitors charged to asymmetrical voltage levels, are used for generating different voltage levels. The SVPWM based control strategy used in this converter maintains the capacitor voltages at the required levels in the entire modulation range including the over-modulation region. For the voltage levels: nine and above, the number of components required in the proposed topology is significantly lower, compared to the conventional multilevel inverter topologies. The number of capacitors required in this topology reduces drastically compared to the conventional flying capacitor topology, when the number of levels in the inverter output increases. This topology has better fault tolerance, as it is capable of operating with reduced number of levels, in the entire modulation range, in the event of any failure in the H-bridges. The transient as well as the steady state performance of the nine-level version of the proposed topology is experimentally verified in the entire modulation range including the over-modulation region.

Minimum switching loss pulse width modulation for reduced power conversion loss in reactive power compensators

Advanced bus-clamping switching sequences, which employ an active vector twice in a subcycle, are used to reduce line current distortion and switching loss in a space vector modulated voltage source converter. This study evaluates minimum switching loss pulse width modulation (MSLPWM), which is a combination of such sequences, for static reactive power compensator (STATCOM) application. It is shown that MSLPWM results in a significant reduction in device loss over conventional space vector pulse width modulation. Experimental verification is presented at different power levels of up to 150 kVA.

An Improved Dead-Time Compensation Scheme for Voltage Source Inverters Considering the Device Switching Transition Times

Inverter dead-time, which is meant to prevent shoot-through fault, causes harmonic distortion and change in the fundamental voltage in the inverter output. Typical dead-time compensation schemes ensure that the amplitude of the fundamental output current is as desired, and also improve the current waveform quality significantly. However, even with compensation, the motor line current waveform is observed to be distorted close to the current zero-crossings. The IGBT switching transition times being significantly longer at low currents than at high currents is an important reason for this zero-crossover distortion. Hence, this paper proposes an improved dead-time compensation scheme, which makes use of the measured IGBT switching transition times at low currents. Measured line current waveforms in a 2.2 kW induction motor drive with the proposed compensation scheme are compared against those with the conventional dead-time compensation scheme and without dead-time compensation. The experimental results on the motor drive clearly demonstrate the improvement in the line current waveform quality with the proposed method.

Thermal test method for high power three-phase grid-connected inverters

Semiconductor device junction temperatures are maintained within datasheet specified limits to avoid failure in power converters. Burn-in tests are used to ensure this. In inverters, thermal time constants can be large and burn-in tests are required to be performed over long durations of time. At higher power levels, besides increased production cost, the testing requires sources and loads that can handle high power. In this study, a novel method to test a high power three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources and loads. Only energy corresponding to the losses is consumed. The test is done by circulating rated current within the three legs of the inverter. All the phase legs being loaded, the method can be used to test the inverter in both cases of a common or independent cooling arrangement for the inverter phase legs. Further, the method can be used with different inverter configurations - three- or four-wire and for different pulse width modulation (PWM) techniques. The method has been experimentally validated on a 24 kVA inverter for a four-wire configuration that uses sine-triangle PWM and a three-wire configuration that uses conventional space vector PWM.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

A 1 V supercapacitor device with nanostructured graphene oxide/polyaniline composite materials

Polyaniline and graphene oxide composite on activated carbon cum reduced graphene oxide-supported supercapacitor electrodes are fabricated and electrochemically characterized in a three-electrode cell assembly. Attractive supercapacitor performance, namely high-power capability and cycling stability for graphene oxide/polyaniline composite, is observed owing to the layered and porous-polymeric-structured electrodes. Based on the materials characterization data in a three-electrode cell assembly, 1 V supercapacitor devices are developed and performance tested. A comparative study has also been conducted for polyaniline and graphene oxide/polyaniline composite-based 1 V supercapacitors for comprehending the synergic effect of graphene oxide and polyaniline. Graphene oxide/polyaniline composite-based capacitor that exhibits about 100 F g(-1) specific capacitance with faradaic efficiency in excess of 90% has its energy and power density values of 14 Wh kg(-1) and 72 kW kg(-1), respectively. Cycle-life data for over 1000 cycles reflect 10% capacitance degradation for graphene oxide/polyaniline composite supercapacitor.

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

Design of a Wearable Remote Neonatal Health Monitoring Device

In this text we present the design of a wearable health monitoring device capable of remotely monitoring health parameters of neonates for the first few weeks after birth. The device is primarily aimed at continuously tracking the skin temperature to indicate the onset of hypothermia in newborns. A medical grade thermistor is responsible for temperature measurement and is directly interfaced to a microcontroller with an integrated bluetooth low energy radio. An inertial sensor is also present in the device to facilitate breathing rate measurement which has been discussed briefly. Sensed data is transferred securely over bluetooth low energy radio to a nearby gateway, which relays the information to a central database for real time monitoring. Low power optimizations at both the circuit and software levels ensure a prolonged battery life. The device is packaged in a baby friendly, water proof housing and is easily sterilizable and reusable.

Low power consumption and high sensitivity carbon monoxide gas sensor using indium oxide nanowire.

In this paper, micro gas sensor was fabricated using indium oxide nanowire for effective gas detection and monitoring system. Indium oxide nanowire was grown using thermal CVD, and their structural properties were examined by the SEM, XRD and TEM. The electric properties for microdropped indium oxide nanowire device were measured, and gas response characteristics were examined for CO gas. Sensors showed high sensitivity and stability for CO gas. And with below 20 mw power consumption, 5 ppm CO could be detected.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

InGaN/GaN LEDs grown on Si(111): Dependence of device performance on threading dislocation density and emission wavelength

We demonstrate the growth of crack-free blue and greenemitting LED structures grown on 2-inch and 6-inch Si(111) substrates by metalorganic vapour phase epitaxy (MOVPE), using AlN nucleation layers and AlGaN buffer layers for stress management. LED device performance and its dependence on threading dislocation (TD) density and emission wavelength were studied. Despite the inherently low light extraction efficiency, an output power of 1.2 mW at 50 mA was measured from a 500 μm square planar device, emitting at 455 nm. The light output decreases dramatically as the emission wavelength increases from 455 nm to 510 nm. For LED devices emitting at similar wavelength, the light output was more than doubled when the TD density was reduced from 5×1 09 cm-2 to 2×109 cm-2. Our results clearly show that high TD density is detrimental to the overall light output, highlighting the need for further TD reduction for structures grown on Si. © 2010 Wiley-VCH Verlag GmbH & Co. KGaA.