Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Efficient analysis, design, and filter applications of EBG waveguide with periodic resonant loads

An efficient analysis and design of an electromagnetic-bandgap (EBG) waveguide with resonant loads is presented. Equivalent-circuit analysis is employed to demonstrate the differences between EBG waveguides with resonant and nonresonant loadings. As a result of the resonance, transmission zeros at finite frequencies emerge. The concept is demonstrated in E-plane waveguides. A generic fast and efficient formulation is presented, which starts from the generalized scattering matrix of the unit cell and derives the dispersion properties of the infinite structure. Both real and imaginary parts of the propagation constant are derived and discussed. The Floquet wavelength and impedance are also presented. The theoretical results are validated by comparison with simulations of a finite structure and experimental results. The application of the proposed EBG waveguide in the suppression of the spurious passband of a conventional E-plane filter is presented by experiment.

Design and analysis of dual-rail circuits for security applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

Investigations on the Analysis and Design of Aperiodic Frequency Selective Surfaces for Space Applications

An investigation on the design of aperiodic FSS is presented. First, an accurate yet efficient method which allows the analysis of finite sized aperiodic FSS has been developed. Subsequently, an optimisation method is implemented which optimises all the FSS elements to obtain an FSS design with an aperiodic element layout. Preliminary designs of aperiodic FSS are presented and the numerical results are discussed.

Smart design of scaffolds obtained by biofabrication for tissue engineering applications

A engenharia de tecidos é um domínio tecnológico emergente em rápido desenvolvimento que se destina a produzir substitutos viáveis para a restauração, manutenção ou melhoria da função dos tecidos ou órgãos humanos. Uma das estratégias mais predominantes em engenharia de tecidos envolve crescimento celular sobre matrizes de suporte (scaffolds), biocompatíveis e biodegradáveis. Estas matrizes devem possuir não só elevadas propriedades mecânicas e vasculares, mas também uma elevada porosidade. Devido à incompatibilidade destes dois parâmetros, é necessário desenvolver estratégias de simulação de forma a obter estruturas optimizadas. A previsão real das propriedades mecânicas, vasculares e topológicas das matrizes de suporte, produzidas por técnicas de biofabricação, é muito importante para as diversas aplicações em engenharia de tecidos. A presente dissertação apresenta o estado da arte da engenharia de tecidos, bem como as técnicas de biofabricação envolvidas na produção de matrizes de suporte. Para o design optimizado de matrizes de suporte foi adoptada uma metodologia de design baseada tanto em métodos de elementos finitos para o cálculo do comportamento mecânico, vascular e as optimizações topológicas, como em métodos analíticos para a validação das simulações estruturais utilizando dados experimentais. Considerando que as matrizes de suporte são estruturas elementares do tipo LEGO, dois tipos de famílias foram consideradas, superfícies não periódicas e as superfícies triplas periódicas que descrevem superfícies naturais. Os objectivos principais desta dissertação são: i) avaliar as técnicas existentes de engenharia de tecidos; ii) avaliar as técnicas existentes de biofabricação para a produção de matrizes de suporte; iii) avaliar o desempenho e comportamento das matrizes de suporte; iv) implementar uma metodologia de design de matrizes de suporte em variáveis tais como a porosidade, geometria e comportamento mecânico e vascular por forma a auxiliar o processo de design; e por fim, v) validar experimentalmente a metodologia adoptada.