FAULT-TOLERANT ALGORITHM FOR HIGH-AVAILABILITY AND WAFER SCALE SYSTEMS.

In this paper, the authors have presented one approach to configuring a Wafer-Scale Integration Chip. The approach described is called the 'WINNER', in which bus channels and an external controller for configuring the working processors are not required. In addition, the technique is applicable to high availability systems constructed using conventional methods. The technique can also be extended to arrays of arbitrary size and with any degree of fault tolerance simply by using an appropriate number of cells.

Whole wafer magnetostriction metrology for magnetic films and multilayers

The requirements for metrology of magnetostriction in complex multilayers and on whole wafers present challenges. An elegant technique based on radius of curvature deformation of whole wafers in a commercial metrology tool is described. The method is based on the Villari effect through application of strain to a film by introducing a radius of curvature. Strain can be applied tensilely and compressively depending on the material. The design, while implemented on 3'' wafers, is scalable. The approach removes effects arising from any shape anisotropy that occurs with smaller samples, which can lead to a change in magnetic response. From the change in the magnetic anisotropy as a function of the radius, saturation magnetostriction ?s can be determined. Dependence on film composition and film thickness was studied to validate the radius of curvature approach with other techniques. ?s decreases from positive values to negative values through an increase in Ni concentration around the permalloy composition, and ?s also increases with a decrease in film thickness, in full agreement with previous reports. We extend the technique by demonstrating the technique applied to a multi-layered structure. These results verify the validity of the method and are an important step to facilitate further work in understanding how manipulation of multilayered films can offer tailored magnetostriction.

Optimal wafer site selection using forward selection component analysis

Reducing wafer metrology continues to be a major target in semiconductor manufacturing efficiency initiatives due to it being a high cost, non-value added operation that impacts on cycle-time and throughput. However, metrology cannot be eliminated completely given the important role it plays in process monitoring and advanced process control. To achieve the required manufacturing precision, measurements are typically taken at multiple sites across a wafer. The selection of these sites is usually based on a priori knowledge of wafer failure patterns and spatial variability with additional sites added over time in response to process issues. As a result, it is often the case that in mature processes significant redundancy can exist in wafer measurement plans. This paper proposes a novel methodology based on Forward Selection Component Analysis (FSCA) for analyzing historical metrology data in order to determine the minimum set of wafer sites needed for process monitoring. The paper also introduces a virtual metrology (VM) based approach for reconstructing the complete wafer profile from the optimal sites identified by FSCA. The proposed methodology is tested and validated on a wafer manufacturing metrology dataset. © 2012 IEEE.

Strained Silicon on Silicon by Wafer Bonding and Layer Transfer from Relaxed SiGe Buffer

We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a relaxed SiGe buffer as a template for inducing tensile strain in a Si layer, which is then bonded to another Si handle wafer. The original Si wafer and the relaxed SiGe buffer are subsequently removed, thereby transferring a strained-Si layer directly to Si substrate without intermediate SiGe or oxide layers. Complete removal of Ge from the structure was confirmed by cross-sectional transmission electron microscopy as well as secondary ion mass spectrometry. A plan-view transmission electron microscopy study of the strained-Si/Si interface reveals that the lattice-mismatch between the layers is accommodated by an orthogonal array of edge dislocations. This misfit dislocation array, which forms upon bonding, is geometrically necessary and has an average spacing of approximately 40nm, in excellent agreement with established dislocation theory. To our knowledge, this is the first study of a chemically homogeneous, yet lattice-mismatched, interface.

Photocatalytic decomposition of methylene blue via Fenton mechanisms by silicon wafer doped with Au and Cu: a theoretical and experimental study

In this work, we studied the photocatalytic and the structural aspects of silicon wafers doped with Au and Cu submitted to thermal treatment. The materials were obtained by deposition of metals on Si using the sputtering method followed by fast heating method. The photocatalyst materials were characterized by synchrotron-grazing incidence X-ray fluorescence, ultraviolet-visible spectroscopy, X-ray diffraction, and assays of H(2)O(2) degradation. The doping process decreases the optical band gap of materials and the doping with Au causes structural changes. The best photocatalytic activity was found for thermally treated material doped with Au. Theoretical calculations at density functional theory level are in agreement with the experimental data.

Preparation of silica abrasives from water glass and application in silicon wafer polishing

Chemical mechanical polishing technique is more frequently adopted for planarization in integrated circuit fabrication. The silica abrasives in colloidal state are fabricated with the sodium silicate solution as raw materials through the polymerization reaction among silicic acid molecules. By continuous injection of silicic acid into the preexisting silica solution, the diameter of silica nanoparticles increases. The different sized silica nanoparticles are imaged by scanning electron microscopy, and the dried silica are characterized by X-ray diffraction and thermal analysis. The polishing test on silicon wafer with as-fabricated silica abrasives shows that the surface flatness reaches 1.1 nm roughness, however, micro scratches are still present in the surface.

Photocatalytic decomposition of methylene blue via Fenton mechanisms by silicon wafer doped with Au and Cu: a theoretical and experimental study

In this work, we studied the photocatalytic and the structural aspects of silicon wafers doped with Au and Cu submitted to thermal treatment. The materials were obtained by deposition of metals on Si using the sputtering method followed by fast heating method. The photocatalyst materials were characterized by synchrotron-grazing incidence X-ray fluorescence, ultraviolet-visible spectroscopy, X-ray diffraction, and assays of H(2)O(2) degradation. The doping process decreases the optical band gap of materials and the doping with Au causes structural changes. The best photocatalytic activity was found for thermally treated material doped with Au. Theoretical calculations at density functional theory level are in agreement with the experimental data.

Mixed-domain simulation and hybrid wafer-level packaging of RF-MEMS devices for wireless applications

In questa tesi verranno trattati sia il problema della creazione di un ambiente di simulazione a domini fisici misti per dispositivi RF-MEMS, che la definizione di un processo di fabbricazione ad-hoc per il packaging e l’integrazione degli stessi. Riguardo al primo argomento, sarà mostrato nel dettaglio lo sviluppo di una libreria di modelli MEMS all’interno dell’ambiente di simulazione per circuiti integrati Cadence c . L’approccio scelto per la definizione del comportamento elettromeccanico dei MEMS è basato sul concetto di modellazione compatta (compact modeling). Questo significa che il comportamento fisico di ogni componente elementare della libreria è descritto per mezzo di un insieme limitato di punti (nodi) di interconnessione verso il mondo esterno. La libreria comprende componenti elementari, come travi flessibili, piatti rigidi sospesi e punti di ancoraggio, la cui opportuna interconnessione porta alla realizzazione di interi dispositivi (come interruttori e capacità variabili) da simulare in Cadence c . Tutti i modelli MEMS sono implementati per mezzo del linguaggio VerilogA c di tipo HDL (Hardware Description Language) che è supportato dal simulatore circuitale Spectre c . Sia il linguaggio VerilogA c che il simulatore Spectre c sono disponibili in ambiente Cadence c . L’ambiente di simulazione multidominio (ovvero elettromeccanico) così ottenuto permette di interfacciare i dispositivi MEMS con le librerie di componenti CMOS standard e di conseguenza la simulazione di blocchi funzionali misti RF-MEMS/CMOS. Come esempio, un VCO (Voltage Controlled Oscillator) in cui l’LC-tank è realizzato in tecnologia MEMS mentre la parte attiva con transistor MOS di libreria sarà simulato in Spectre c . Inoltre, nelle pagine successive verrà mostrata una soluzione tecnologica per la fabbricazione di un substrato protettivo (package) da applicare a dispositivi RF-MEMS basata su vie di interconnessione elettrica attraverso un wafer di Silicio. La soluzione di packaging prescelta rende possibili alcune tecniche per l’integrazione ibrida delle parti RF-MEMS e CMOS (hybrid packaging). Verranno inoltre messe in luce questioni riguardanti gli effetti parassiti (accoppiamenti capacitivi ed induttivi) introdotti dal package che influenzano le prestazioni RF dei dispositivi MEMS incapsulati. Nel dettaglio, tutti i gradi di libertà del processo tecnologico per l’ottenimento del package saranno ottimizzati per mezzo di un simulatore elettromagnetico (Ansoft HFSSTM) al fine di ridurre gli effetti parassiti introdotti dal substrato protettivo. Inoltre, risultati sperimentali raccolti da misure di strutture di test incapsulate verranno mostrati per validare, da un lato, il simulatore Ansoft HFSSTM e per dimostrate, dall’altro, la fattibilit`a della soluzione di packaging proposta. Aldilà dell’apparente debole legame tra i due argomenti sopra menzionati è possibile identificare un unico obiettivo. Da un lato questo è da ricercarsi nello sviluppo di un ambiente di simulazione unificato all’interno del quale il comportamento elettromeccanico dei dispositivi RF-MEMS possa essere studiato ed analizzato. All’interno di tale ambiente, l’influenza del package sul comportamento elettromagnetico degli RF-MEMS può essere tenuta in conto per mezzo di modelli a parametri concentrati (lumped elements) estratti da misure sperimentali e simulazioni agli Elementi Finiti (FEM) della parte di package. Infine, la possibilità offerta dall’ambiente Cadence c relativamente alla simulazione di dipositivi RF-MEMS interfacciati alla parte CMOS rende possibile l’analisi di blocchi funzionali ibridi RF-MEMS/CMOS completi.

Analysis of Synthetic Diamond Wafer Interferograms Using a Parallelized Simulated Annealing Algorithm

Diamonds are known for both their beauty and their durability. Jefferson National Lab in Newport News, VA has found a way to utilize the diamond's strength to view the beauty of the inside of the atomic nucleus with the hopes of finding exotic forms of matter. By firing very fast electrons at a diamond sheet no thicker than a human hair, high energy particles of light known as photons are produced with a high degree of polarization that can illuminate the constituents of the nucleus known as quarks. The University of Connecticut Nuclear Physics group has responsibility for crafting these extremely thin, high quality diamond wafers. These wafers must be cut from larger stones that are about the size of a human finger, and then carefully machined down to the final thickness. The thinning of these diamonds is extremely challenging, as the diamond's greatest strength also becomes its greatest weakness. The Connecticut Nuclear Physics group has developed a novel technique to assist industrial partners in assessing the quality of the final machining steps, using a technique based on laser interferometry. The images of the diamond surface produced by the interferometer encode the thickness and shape of the diamond surface in a complex way that requires detailed analysis to extract. We have developed a novel software application to analyze these images based on the method of simulated annealing. Being able to image the surface of these diamonds without requiring costly X-ray diffraction measurements allows rapid feedback to the industrial partners as they refine their thinning techniques. Thus, by utilizing a material found to be beautiful by many, the beauty of nature can be brought more clearly into view.

Full-Wafer Roller-NIL Processes for Silicon Solar Cell Texturisation

The highest solar cell efficiencies both for c-Si and mc-Si were reached using template based texturing processes. Especially for mc-Si the benefit of a defined texture, the so called honeycomb texture, was demonstrated impressively. However, up until now, no industrially feasible process has been available to pattern the necessary etching masks with the sufficient resolution. Roller-Nanoimprint Lithography (Roller-NIL) has the potential to overcome these limitations and to allow high quality pattern transfers, even in the sub-micron regime, in continuous in-line processes. Therefore, this etch-mask patterning technique is a suitable solution to bring such elaborate features like the honeycomb texture to an industrial realization. Beyond that, this fast printing-like technology opens up new possibilities to introduce promising concepts like photonic structures into solar cells.

About the origin of low wafer performance and crystal defect generation on seed-cast growth of industrial mono-like silicon ingots

The era of the seed-cast grown monocrystalline-based silicon ingots is coming. Mono-like, pseudomono or quasimono wafers are product labels that can be nowadays found in the market, as a critical innovation for the photovoltaic industry. They integrate some of the most favorable features of the conventional silicon substrates for solar cells, so far, such as the high solar cell efficiency offered by the monocrystalline Czochralski-Si (Cz-Si) wafers and the lower cost, high productivity and full square-shape that characterize the well-known multicrystalline casting growth method. Nevertheless, this innovative crystal growth approach still faces a number of mass scale problems that need to be resolved, in order to gain a deep, 100% reliable and worldwide market: (i) extended defects formation during the growth process; (ii) optimization of the seed recycling; and (iii) parts of the ingots giving low solar cells performance, which directly affect the production costs and yield of this approach. Therefore, this paper presents a series of casting crystal growth experiments and characterization studies from ingots, wafers and cells manufactured in an industrial approach, showing the main sources of crystal defect formation, impurity enrichment and potential consequences at solar cell level. The previously mentioned technological drawbacks are directly addressed, proposing industrial actions to pave the way of this new wafer technology to high efficiency solar cells.