951 resultados para Reconfigurable antenna


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Dispersion characteristics and topography of electromagnetic fields of axially symmetric surface waves (SW) and of azimuth surface waves (ASW) propagating in a structure composed of a cylindrical metal antenna and magnetoactive plasma are investigated. The antenna and plasma may be separated by a vacuum layer. The dispersion characteristics of SW and ASW are presented as functions of the antenna and the magnetoactive plasma parameters. Close agreement between theory and experimental results are shown. Surface impedances of the SW and ASW are calculated for various parameters of the problem.

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The structure of a microwave gas discharge produced and sustained by a surface wave (SW) propagating along a cylindrical metal antenna with a dielectric coating is studied. The SW that produces and sustains the microwave gas discharge propagates along an external magnetic field and has an eigenfrequency in the range between the electron cyclotron and electron plasma frequencies. The presence of a dielectric (vacuum) sheath region separating the antenna from the plasma is assumed. The spatial distributions of the produced plasma density, electromagnetic fields, energy flow density, phase velocity and reverse skin depth of the SW are obtained analytically and numerically.

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Antenna arrays are groups of antenna elements spaced in a geometrical pattern. By changing the phase excitation of each element, the array is capable of transmitting electromagnetic waves strongly in a chosen direction with little or no radiation in another direction, thus controlling the array's radiation pattern without physically moving any parts. An antenna array of sub-arrays replaces conventional antenna elements with compact circular arrays with potential for improved performance. This thesis expands on the concept by exploring the development, realisation and operation of an array of subarrays. The overall size of the array essentially remains the same, but the array's performance is improved due to having steerable directive subarrays. The negative effects of strong mutual coupling between closely spaced elements of a subarray are analysed and a number of new solutions for element decoupling are proposed.

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An opportunistic relay selection scheme improving cooperative diversity is devised using the concept of a virtual SIMO-MISO antenna array. By incorporating multiple users as a virtual distributed antenna, not only helps combat fading but also provides significant advantage in terms of energy consumption. The proposed efficient multiple relay selection uses the concept of the distributed Alamouti scheme in a time varying environment to realize cooperative networking in wireless relay networks and provides the platform for outage, Diversiy-Multiplexing Tradeoff (DMT) and Bit-Error-Rate (BER) analysis to conclude that it is capable of achieving promising diversity gains by operating at much lower SNR when compared with conventional relay selection methods. It also has the added advantage of conserving energy for the relays that are reachable but not selected for the cooperative communication.

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This research project investigated and designed a modular architecture for a 3D Reconfigurable Autopilot Flight System that could be used to control actuators in both manned and unmanned aircraft. The system is based on a CAN Bus interface and allows seamless control of different types of actuators. During the course of the research the differences and similarities of autopilots for fixed-wing general aviation aircraft and unmanned aircraft were analysed focusing on the actuator interfaces. This project suggests that software and hardware used in commercial-of-the-shelf avionics could be used in manned and unmanned aviation.

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This research study investigates the application of phase shifter-based smart antenna system in distributed beamforming. It examines the way to optimise the transmit power by jointly maximising the directivity of the array antennas and the weight vector for distributed beamforming. This research study concludes that maximising directivity can lead to better transmit power minimisation compared to maximising field intensity. This study also concludes that signal to noise power ratio maximisation subject to a power constraint and power minimisation subject to a signal to noise power ratio constraint yield the same results.

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Monitoring pedestrian and cyclists movement is an important area of research in transport, crowd safety, urban design and human behaviour assessment areas. Media Access Control (MAC) address data has been recently used as potential information for extracting features from people’s movement. MAC addresses are unique identifiers of WiFi and Bluetooth wireless technologies in smart electronics devices such as mobile phones, laptops and tablets. The unique number of each WiFi and Bluetooth MAC address can be captured and stored by MAC address scanners. MAC addresses data in fact allows for unannounced, non-participatory, and tracking of people. The use of MAC data for tracking people has been focused recently for applying in mass events, shopping centres, airports, train stations etc. In terms of travel time estimation, setting up a scanner with a big value of antenna’s gain is usually recommended for highways and main roads to track vehicle’s movements, whereas big gains can have some drawbacks in case of pedestrian and cyclists. Pedestrian and cyclists mainly move in built distinctions and city pathways where there is significant noises from other fixed WiFi and Bluetooth. Big antenna’s gains will cover wide areas that results in scanning more samples from pedestrians and cyclists’ MAC device. However, anomalies (such fixed devices) may be captured that increase the complexity and processing time of data analysis. On the other hand, small gain antennas will have lesser anomalies in the data but at the cost of lower overall sample size of pedestrian and cyclist’s data. This paper studies the effect of antenna characteristics on MAC address data in terms of travel-time estimation for pedestrians and cyclists. The results of the empirical case study compare the effects of small and big antenna gains in order to suggest optimal set up for increasing the accuracy of pedestrians and cyclists’ travel-time estimation.

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In this paper we propose a circularly polarized (CP) microstrip antenna on a suspended substrate with a coplanar capacitive feed and a slot within the rectangular patch. The antenna has an axial ratio bandwidth (< 3 dB) of 7.1%. The proposed antenna exhibits a much higher impedance bandwidth of about 49% (S11 < -10 dB) and also yields return loss better than -15 dB in the useful range of circular polarization. Measured characteristics of the antenna are in good agreement with the simulated results. The radiation patterns indicate good cross polarization rejection and low back lobe radiations. The design proposed here can be scaled to any frequency of interest.

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Distributed space time coding for wireless relay networks when the source, the destination and the relays have multiple antennas have been studied by Jing and Hassibi. In this set-up, the transmit and the receive signals at different antennas of the same relay are processed and designed independently, even though the antennas are colocated. In this paper, a wireless relay network with single antenna at the source and the destination and two antennas at each of the R relays is considered. A new class of distributed space time block codes called Co-ordinate Interleaved Distributed Space-Time Codes (CIDSTC) are introduced where, in the first phase, the source transmits a T-length complex vector to all the relays;and in the second phase, at each relay, the in-phase and quadrature component vectors of the received complex vectors at the two antennas are interleaved and processed before forwarding them to the destination. Compared to the scheme proposed by Jing-Hassibi, for T >= 4R, while providing the same asymptotic diversity order of 2R, CIDSTC scheme is shown to provide asymptotic coding gain with the cost of negligible increase in the processing complexity at the relays. However, for moderate and large values of P, CIDSTC scheme is shown to provide more diversity than that of the scheme proposed by Jing-Hassibi. CIDSTCs are shown to be fully diverse provided the information symbols take value from an appropriate multidimensional signal set.

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The current study reports the synthesis and properties of a novel isoindoline nitroxide contg. a benzophenone chromophore fused into the carbon framework. When exposed to UV light, rather than undergoing traditional benzophenone photochem. pathways, the presence of the nitroxide enables an energy transfer process whereby the nitroxide enters an excited state which induces an efficient hydrogen atom transfer from unactivated alkanes.

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We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

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In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.

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This paper presents a generalized approach to design an electromagnetically coupled microstrip ring antenna for dual-band operation. By widening two opposite sides of a square ring antenna, its fractional bandwidth at the primary resonance mode can be increased significantly so that it may be used for practical applications. By attaching a stub to the inner edge of the side opposite to the feed arm, some of the losses in electrical length caused by widening can be regained. More importantly, this addition also alters the current distribution on the antenna and directs radiations at the second resonant frequency towards boresight. It has also been observed that for the dual frequency configurations studied, the ratio of the resonant frequencies (center dot r(2)center dot center dot r(1)) can range between 1.55 and 2.01. This shows flexibility in designing dual frequency antennas with a desired pair of resonant frequencies.

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Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.