A peak reduction scheduling algorithm for storage devices on the low voltage network

Reinforcing the Low Voltage (LV) distribution network will become essential to ensure it remains within its operating constraints as demand on the network increases. The deployment of energy storage in the distribution network provides an alternative to conventional reinforcement. This paper presents a control methodology for energy storage to reduce peak demand in a distribution network based on day-ahead demand forecasts and historical demand data. The control methodology pre-processes the forecast data prior to a planning phase to build in resilience to the inevitable errors between the forecasted and actual demand. The algorithm uses no real time adjustment so has an economical advantage over traditional storage control algorithms. Results show that peak demand on a single phase of a feeder can be reduced even when there are differences between the forecasted and the actual demand. In particular, results are presented that demonstrate when the algorithm is applied to a large number of single phase demand aggregations that it is possible to identify which of these aggregations are the most suitable candidates for the control methodology.

The impact of location and type on the performance of Low-Voltage network connected Battery Energy Storage Systems

This paper assesses the impact of the location and configuration of Battery Energy Storage Systems (BESS) on Low-Voltage (LV) feeders. BESS are now being deployed on LV networks by Distribution Network Operators (DNOs) as an alternative to conventional reinforcement (e.g. upgrading cables and transformers) in response to increased electricity demand from new technologies such as electric vehicles. By storing energy during periods of low demand and then releasing that energy at times of high demand, the peak demand of a given LV substation on the grid can be reduced therefore mitigating or at least delaying the need for replacement and upgrade. However, existing research into this application of BESS tends to evaluate the aggregated impact of such systems at the substation level and does not systematically consider the impact of the location and configuration of BESS on the voltage profiles, losses and utilisation within a given feeder. In this paper, four configurations of BESS are considered: single-phase, unlinked three-phase, linked three-phase without storage for phase-balancing only, and linked three-phase with storage. These four configurations are then assessed based on models of two real LV networks. In each case, the impact of the BESS is systematically evaluated at every node in the LV network using Matlab linked with OpenDSS. The location and configuration of a BESS is shown to be critical when seeking the best overall network impact or when considering specific impacts on voltage, losses, or utilisation separately. Furthermore, the paper also demonstrates that phase-balancing without energy storage can provide much of the gains on unbalanced networks compared to systems with energy storage.

Low voltage and variable-pressure scanning electron microscopy of fractured composites

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Low voltage analog synthesizer of orthogonal signals: A current-mode approach

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Experimental results using 0.35 mu m AMS CMOS process are presented for generation of the cosine and Legendre basis.

Low voltage analog synthesizer of orthogonal signals using current mode techniques

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Simulation results using 0.35 mu m AMS CMOS process are presented for generation of the cosine and Legendre basis.

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Low-voltage varistor based on (Sn,Ti)O-2 ceramics

A description is given of the nonohmic behavior obtained in (SnxTi1-x)O-2-based systems. A matrix founded on (SnxTi1-x)O-2-based systems doped with Nb2O5 leads to a low-voltage varistor system with nonlinear coefficient values of similar to9. The presence of the back-to-back Schottky-type barrier is observed based on the voltage dependence of the capacitance. When doped with CoO, the (SnxTi1-x)O(2)(.)based system presents higher nonlinear coefficient values (>30) than does the SnO2-based varistor system.

A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

PROCESSING AND CHARACTERIZATION OF LOW-VOLTAGE VARISTORS

ZnO seed particles and Cr2O3 were used in this study to control the microstructure of ZnO varistors. The seed particles were prepared by adding 1.0 mol % BaO to ZnO. The powder was then calcined at 800-degrees-C for 2 h, pressed into pellets and sintered at 1400-degrees-C for 8 h. The sintered ZnO was ground and the BaO eliminated by washing in water. The remaining ZnO powder was classified into a size fraction ranging from 38 to 149 mum. The addition of a small amount (1 weight %) ZnO seed grains produces varistors with low breakdown voltages (7.6 V/mm) and an alpha coefficient of approximately 10. The addition of Cr2O3 stabilizes the spinel phase yielding a more homogeneous microstructure, but degraded electrical behaviour of the ZnO varistor.

A CMOS/SOI single-input PWM discriminator for low-voltage body-implanted applications

A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Low voltage electroluminescence of terbium- and thulium-doped zinc oxide films

Strong interest in developing technology for visual information. stimulates research for thin film electroluminescent devices. Here, for the first time, we report that thulium- and terbium-doped zinc-oxide films are suitable for electroluminescence applications. Two different devices were assembled as lTO/LiF/ZnO:RE/LiF/Al or ITO/SiO2/ZnO:RE/SiO2/Al, where ZnO:RE is a film of zinc oxide containing 10 at% of Tb3+ or Tm3+. Electroluminescence spectra show that besides a broad emission band with maximum around 650 nm assigned to ZnO, also emission lines from Tb3+ at 484 nm (D-5(4) -> F-7(6)), 543 nm (D-5(4) -> F-7(6)), and 589 nm (D-5(4) -> F-7(4)), or from Tm3+ at 478 nm ((1)G(4) -> H-3(6)), and 511 mn (D-1(2) -> H-3(5)) were detected. Intensity of emission as function of applied voltage and current-voltage characteristic are shown and discussed. (c) 2005 Elsevier B.V. All rights reserved.

A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to (gm)-C filters

A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.

The effect of TiO(2) on the microstructural and electrical properties of low voltage varistor based on (Sn,Ti)O(2) ceramics

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)