Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
| Contribuinte(s) |
Universidade Estadual Paulista (UNESP) |
|---|---|
| Data(s) |
20/05/2014
20/05/2014
01/01/2007
|
| Resumo |
Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz. |
| Formato |
52-55 |
| Identificador |
http://dx.doi.org/10.1109/DTIS.2007.4449491 2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007. http://hdl.handle.net/11449/9689 10.1109/DTIS.2007.4449491 WOS:000256296500010 |
| Idioma(s) |
eng |
| Publicador |
IEEE |
| Relação |
2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era |
| Direitos |
closedAccess |
| Tipo |
info:eu-repo/semantics/conferencePaper |
