Redox Control of 20S Proteasome Gating

The proteasome is the primary contributor in intracellular proteolysis. Oxidized or unstructured proteins can be degraded via a ubiquitin-and ATP-independent process by the free 20S proteasome (20SPT). The mechanism by which these proteins enter the catalytic chamber is not understood thus far, although the 20SPT gating conformation is considered to be an important barrier to allowing proteins free entrance. We have previously shown that S-glutathiolation of the 20SPT is a post-translational modification affecting the proteasomal activities. Aims: The goal of this work was to investigate the mechanism that regulates 20SPT activity, which includes the identification of the Cys residues prone to S-glutathiolation. Results: Modulation of 20SPT activity by proteasome gating is at least partially due to the S-glutathiolation of specific Cys residues. The gate was open when the 20SPT was S-glutathiolated, whereas following treatment with high concentrations of dithiothreitol, the gate was closed. S-glutathiolated 20SPT was more effective at degrading both oxidized and partially unfolded proteins than its reduced form. Only 2 out of 28 Cys were observed to be S-glutathiolated in the proteasomal alpha 5 subunit of yeast cells grown to the stationary phase in glucose-containing medium. Innovation: We demonstrate a redox post-translational regulatory mechanism controlling 20SPT activity. Conclusion: S-glutathiolation is a post-translational modification that triggers gate opening and thereby activates the proteolytic activities of free 20SPT. This process appears to be an important regulatory mechanism to intensify the removal of oxidized or unstructured proteins in stressful situations by a process independent of ubiquitination and ATP consumption. Antioxid. Redox Signal. 16, 1183-1194.

A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration

Purpose - The purpose of this paper is to develop an efficient numerical algorithm for the self-consistent solution of Schrodinger and Poisson equations in one-dimensional systems. The goal is to compute the charge-control and capacitance-voltage characteristics of quantum wire transistors. Design/methodology/approach - The paper presents a numerical formulation employing a non-uniform finite difference discretization scheme, in which the wavefunctions and electronic energy levels are obtained by solving the Schrodinger equation through the split-operator method while a relaxation method in the FTCS scheme ("Forward Time Centered Space") is used to solve the two-dimensional Poisson equation. Findings - The numerical model is validated by taking previously published results as a benchmark and then applying them to yield the charge-control characteristics and the capacitance-voltage relationship for a split-gate quantum wire device. Originality/value - The paper helps to fulfill the need for C-V models of quantum wire device. To do so, the authors implemented a straightforward calculation method for the two-dimensional electronic carrier density n(x,y). The formulation reduces the computational procedure to a much simpler problem, similar to the one-dimensional quantization case, significantly diminishing running time.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Bit noise from an optical logic gate with laser diodes

Output bits from an optical logic cell present noise due to the type of technique used to obtain the Boolean functions of two input data bits. We have simulated the behavior of an optically programmable logic cell working with Fabry Perot-laser diodes of the same type employed in optical communications (1550nm) but working here as amplifiers. We will report in this paper a study of the bit noise generated from the optical non-linearity process allowing the Boolean function operation of two optical input data signals. Two types of optical logic cells will be analyzed. Firstly, a classical "on-off" behavior, with transmission operation of LD amplifier and, secondly, a more complicated configuration with two LD amplifiers, one working on transmission and the other one in reflection mode. This last configuration has nonlinear behavior emulating SEED-like properties. In both cases, depending on the value of a "1" input data signals to be processed, a different logic function can be obtained. Also a CW signal, known as control signal, may be apply to fix the type of logic function. The signal to noise ratio will be analyzed for different parameters, as wavelength signals and the hysteresis cycles regions associated to the device, in relation with the signals power level applied. With this study we will try to obtain a better understanding of the possible effects present on an optical logic gate with Laser Diodes.

Characteristic study, its identification and self-tuned approach to control hydro-power plants

The water time constant and mechanical time constant greatly influences the power and speed oscillations of hydro-turbine-generator unit. This paper discusses the turbine power transients in response to different nature and changes in the gate position. The work presented here analyses the characteristics of hydraulic system with an emphasis on changes in the above time constants. The simulation study is based on mathematical first-, second-, third- and fourth-order transfer function models. The study is further extended to identify discrete time-domain models and their characteristic representation without noise and with noise content of 10 & 20 dB signal-to-noise ratio (SNR). The use of self-tuned control approach in minimising the speed deviation under plant parameter changes and disturbances is also discussed.

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

BIDIRECTIONAL AC-DC CONVERTERS USING ONE CYCLE CONTROL (OCC) FOR ELECTRIC VEHICLES

The electric vehicle (EV) market has seen a rapid growth in the recent past. With an increase in the number of electric vehicles on road, there is an increase in the number of high capacity battery banks interfacing the grid. The battery bank of an EV, besides being the fuel tank, is also a huge energy storage unit. Presently, it is used only when the vehicle is being driven and remains idle for rest of the time, rendering it underutilized. Whereas on the other hand, there is a need of large energy storage units in the grid to filter out the fluctuations of supply and demand during a day. EVs can help bridge this gap. The EV battery bank can be used to store the excess energy from the grid to vehicle (G2V) or supply stored energy from the vehicle to grid (V2G ), when required. To let power flow happen, in both directions, a bidirectional AC-DC converter is required. This thesis concentrates on the bidirectional AC-DC converters which have a control on power flow in all four quadrants for the application of EV battery interfacing with the grid. This thesis presents a bidirectional interleaved full bridge converter topology. This helps in increasing the power processing and current handling capability of the converter which makes it suitable for the purpose of EVs. Further, the benefit of using the interleaved topology is that it increases the power density of the converter. This ensures optimization of space usage with the same power handling capacity. The proposed interleaved converter consists of two full bridges. The corresponding gate pulses of each switch, in one cell, are phase shifted by 180 degrees from those of the other cell. The proposed converter control is based on the one-cycle controller. To meet the challenge of new requirements of reactive power handling capabilities for grid connected converters, posed by the utilities, the controller is modified to make it suitable to process the reactive power. A fictitious current derived from the grid voltage is introduced in the controller, which controls the converter performance. The current references are generated using the second order generalized integrators (SOGI) and phase locked loop (PLL). A digital implementation of the proposed control ii scheme is developed and implemented using DSP hardware. The simulated and experimental results, based on the converter topology and control technique discussed here, are presented to show the performance of the proposed theory.

Comparison of linear optics quantum-computation control-sign gates with ancilla inefficiency and an improvement to functionality under these conditions

We compare three proposals for nondeterministic control-sign gates implemented using linear optics and conditional measurements with nonideal ancilla mode production and detection. The simplified Knill-Laflamme-Milburn gate [Ralph , Phys. Rev. A 65, 012314 (2001)] appears to be the most resilient under these conditions. We also find that the operation of this gate can be improved by adjusting the beam splitter ratios to compensate to some extent for the effects of the imperfect ancilla.

Optimal control, geometry, and quantum computing

We prove upper and lower bounds relating the quantum gate complexity of a unitary operation, U, to the optimal control cost associated to the synthesis of U. These bounds apply for any optimal control problem, and can be used to show that the quantum gate complexity is essentially equivalent to the optimal control cost for a wide range of problems, including time-optimal control and finding minimal distances on certain Riemannian, sub-Riemannian, and Finslerian manifolds. These results generalize the results of [Nielsen, Dowling, Gu, and Doherty, Science 311, 1133 (2006)], which showed that the gate complexity can be related to distances on a Riemannian manifold.

Species differential regulation of COX2 can be described by an NFκB-dependent logic AND gate

Cyclooxygenase 2 (COX2), a key regulatory enzyme of the prostaglandin/eicosanoid pathway, is an important target for anti-inflammatory therapy. It is highly induced by pro-inflammatory cytokines in a Nuclear factor kappa B (NFκB)-dependent manner. However, the mechanisms determining the amplitude and dynamics of this important pro-inflammatory event are poorly understood. Furthermore, there is significant difference between human and mouse COX2 expression in response to the inflammatory stimulus tumor necrosis factor alpha (TNFα). Here, we report the presence of a molecular logic AND gate composed of two NFκB response elements (NREs) which controls the expression of human COX2 in a switch-like manner. Combining quantitative kinetic modeling and thermostatistical analysis followed by experimental validation in iterative cycles, we show that the human COX2 expression machinery regulated by NFκB displays features of a logic AND gate. We propose that this provides a digital, noise-filtering mechanism for a tighter control of expression in response to TNFα, such that a threshold level of NFκB activation is required before the promoter becomes active and initiates transcription. This NFκB-regulated AND gate is absent in the mouse COX2 promoter, most likely contributing to its differential graded response in promoter activity and protein expression to TNFα. Our data suggest that the NFκB-regulated AND gate acts as a novel mechanism for controlling the expression of human COX2 to TNFα, and its absence in the mouse COX2 provides the foundation for further studies on understanding species-specific differential gene regulation.

BIDIRECTIONAL AC-DC CONVERTERS USING ONE CYCLE CONTROL (OCC) FOR ELECTRIC VEHICLES

The electric vehicle (EV) market has seen a rapid growth in the recent past. With an increase in the number of electric vehicles on road, there is an increase in the number of high capacity battery banks interfacing the grid. The battery bank of an EV, besides being the fuel tank, is also a huge energy storage unit. Presently, it is used only when the vehicle is being driven and remains idle for rest of the time, rendering it underutilized. Whereas on the other hand, there is a need of large energy storage units in the grid to filter out the fluctuations of supply and demand during a day. EVs can help bridge this gap. The EV battery bank can be used to store the excess energy from the grid to vehicle (G2V) or supply stored energy from the vehicle to grid (V2G ), when required. To let power flow happen, in both directions, a bidirectional AC-DC converter is required. This thesis concentrates on the bidirectional AC-DC converters which have a control on power flow in all four quadrants for the application of EV battery interfacing with the grid. This thesis presents a bidirectional interleaved full bridge converter topology. This helps in increasing the power processing and current handling capability of the converter which makes it suitable for the purpose of EVs. Further, the benefit of using the interleaved topology is that it increases the power density of the converter. This ensures optimization of space usage with the same power handling capacity. The proposed interleaved converter consists of two full bridges. The corresponding gate pulses of each switch, in one cell, are phase shifted by 180 degrees from those of the other cell. The proposed converter control is based on the one-cycle controller. To meet the challenge of new requirements of reactive power handling capabilities for grid connected converters, posed by the utilities, the controller is modified to make it suitable to process the reactive power. A fictitious current derived from the grid voltage is introduced in the controller, which controls the converter performance. The current references are generated using the second order generalized integrators (SOGI) and phase locked loop (PLL). A digital implementation of the proposed control ii scheme is developed and implemented using DSP hardware. The simulated and experimental results, based on the converter topology and control technique discussed here, are presented to show the performance of the proposed theory.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Water Delivery Quality and Automatic Control Modes in Irrigation Canals. A Case Study.

Regarding canal management modernization, water savings and water delivery quality, the study presents two automatic canal control approaches of the PI (Proportional and Integral) type: the distant and the local downstream control modes. The two PI controllers are defined, tuned and tested using an hydraulic unsteady flow simulation model, particularly suitable for canal control studies. The PI control parameters are tuned using optimization tools. The simulations are done for a Portuguese prototype canal and the PI controllers are analyzed and compared considering a demand-oriented-canal operation. The paper presents and analyzes the two control modes answers for five different offtake types – gate controlled weir, gate controlled orifice, weir with or without adjustable height and automatic flow adjustable offtake. The simulation results are compared using water volumes performance indicators (considering the demanded, supplied and the effectives water volumes) and a time indicator, defined taking into account the time during which the demand discharges are effective discharges. Regarding water savings, the simulation results for the five offtake types prove that the local downstream control gives the best results (no water operational losses) and that the distant downstream control presents worse results in connection with the automatic flow adjustable offtakes. Considering the water volumes and time performance indicators, the best results are obtained for the automatic flow adjustable offtakes and the worse for the gate controlled orifices, followed by the weir with adjustable height.