Hybrid three-phase HPF rectifier with programmable input current THD, using FPGA device and VHDL language

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. Finally, the proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. The proposed strategy is verified by experiments. �� 2008 IEEE.

Reconfigurable IEEE1451-FPGA based weblab infrastructure

Weblabs are spreading their influence in Science and Engineering (S&E) courses providing a way to remotely conduct real experiments. Typically, they are implemented by different architectures and infrastructures supported by Instruments and Modules (I&Ms) able to be remotely controlled and observed. Besides the inexistence of a standard solution for implementing weblabs, their reconfiguration is limited to a setup procedure that enables interconnecting a set of preselected I&Ms into an Experiment Under Test (EUT). Moreover, those I&Ms are not able to be replicated or shared by different weblab infrastructures, since they are usually based on hardware platforms. Thus, to overcome these limitations, this paper proposes a standard solution that uses I&Ms embedded into Field-Programmable Gate Array (FPGAs) devices. It is presented an architecture based on the IEEE1451.0 Std. supported by a FPGA-based weblab infrastructure able to be remotely reconfigured with I&Ms, described through standard Hardware Description Language (HDL) files, using a Reconfiguration Tool (RecTool).

Sistema did��ctico de baixo custo com FPGA de alta densidade

O uso das Field-Programmable Gate Array tem crescido de forma exponencial. Com isto dito, �� importante que os engenheiros electrot��cnicos estejam familiarizados com este tipo de tecnologia. Foi com o intu��do de passar estas val��ncias para os alunos do ISEP, que surgiu a ideia de criar um sistema did��ctico, que permitisse ao alunos aprender a trabalhar com estes dispositivos. O seguinte trabalho iniciou-se com base num estudo das caracter��sticas destes dispositivos e das suas potencialidades, seguido de uma avalia����o do que o mercado tem para oferecer. Posteriormente, com base em toda a informa����o reunida, foi definida a arquitectura do sistema, que levou selec����o de dispositivos a incluir no mesmo, e culminando na concep����o do esquema el��ctrico do sistema e da placa de circuito impresso correspondente ao prot��tipo do mesmo. As principais directivas para este projecto foram o uso de uma FPGA de alta densidade e a concep����o da ferramenta com o custo de projecto o mais reduzido poss��vel.

Controlo de conversores de pot��ncia gen��ricos por FPGA

Disserta����o para obten����o do grau de Mestre em Engenharia Eletrot��cnica Ramo de Automa����o e Eletr��nica Industrial

FPGA-Based Control Design for Power Electronic Applications

Tehoelektoniikkalaitteella tarkoitetaan ohjaus- ja s����t��j��rjestelm����, jolla s��hk���� muokataan saatavilla olevasta muodosta haluttuun uuteen muotoon ja samalla hallitaan s��hk��isen tehon virtausta l��hteest�� k��ytt��kohteeseen. T��m�� siis eroaa signaalielektroniikasta, jossa s��hk��ll�� tyypillisesti siirret����n tietoa hy��dynt��en eri tiloja. Tehoelektroniikkalaitteita vertailtaessa katsotaan yleens�� niiden luotettavuutta, kokoa, tehokkuutta, s����t��tarkkuutta ja tietysti hintaa. Tyypillisi�� tehoelektroniikkalaitteita ovat taajuudenmuuttajat, UPS (Uninterruptible Power Supply) -laitteet, hitsauskoneet, induktiokuumentimet sek�� erilaiset tehol��hteet. Perinteisesti n��iden laitteiden ohjaus toteutetaan k��ytt��en mikroprosessoreja, ASIC- (Application Specific Integrated Circuit) tai IC (Intergrated Circuit) -piirej�� sek�� analogisia s����timi��. T��ss�� tutkimuksessa on analysoitu FPGA (Field Programmable Gate Array) -piirien soveltuvuutta tehoelektroniikan ohjaukseen. FPGA-piirien rakenne muodostuu erilaisista loogisista elementeist�� ja niiden v��lisist�� yhdysjohdoista.Loogiset elementit ovat porttipiirej�� ja kiikkuja. Yhdysjohdot ja loogiset elementit ovat piiriss�� kiinteit�� eik�� koostumusta tai lukum����r���� voi j��lkik��teen muuttaa. Ohjelmoitavuus syntyy elementtien v��lisist�� liit��nn��ist��. Piiriss�� on lukuisia, jopa miljoonia kytkimi��, joiden asento voidaan asettaa. Siten piirin peruselementeist�� voidaan muodostaa lukematon m����r�� erilaisia toiminnallisia kokonaisuuksia. FPGA-piirej�� on pitk����n k��ytetty kommunikointialan tuotteissa ja siksi niiden kehitys on viime vuosina ollut nopeaa. Samalla hinnat ovat pudonneet. T��st�� johtuen FPGA-piirist�� on tullut kiinnostava vaihtoehto my��s tehoelektroniikkalaitteiden ohjaukseen. V��it��sty��ss�� FPGA-piirien k��yt��n soveltuvuutta on tutkittu k��ytt��en kahta vaativaa ja erilaista k��yt��nn��n tehoelektroniikkalaitetta: taajuudenmuuttajaa ja hitsauskonetta. Molempiin testikohteisiin rakennettiin alan suomalaisten teollisuusyritysten kanssa soveltuvat prototyypit,joiden ohjauselektroniikka muutettiin FPGA-pohjaiseksi. Lis��ksi kehitettiin t��t�� uutta tekniikkaa hy��dynt��v��t uudentyyppiset ohjausmenetelm��t. Prototyyppien toimivuutta verrattiin vastaaviin perinteisill�� menetelmill�� ohjattuihin kaupallisiin tuotteisiin ja havaittiin FPGA-piirien mahdollistaman rinnakkaisen laskennantuomat edut molempien tehoelektroniikkalaitteiden toimivuudessa. Ty��ss�� on my��sesitetty uusia menetelmi�� ja ty��kaluja FPGA-pohjaisen s����t��j��rjestelm��n kehitykseen ja testaukseen. Esitetyill�� menetelmill�� tuotteiden kehitys saadaan mahdollisimman nopeaksi ja tehokkaaksi. Lis��ksi ty��ss�� on kehitetty FPGA:n sis��inen ohjaus- ja kommunikointiv��yl��rakenne, joka palvelee tehoelektroniikkalaitteiden ohjaussovelluksia. Uusi kommunikointirakenne edist���� lis��ksi jo tehtyjen osaj��rjestelmien uudelleen k��ytett��vyytt�� tulevissa sovelluksissa ja tuotesukupolvissa.

Exploring carrier agents in swarm-array computing

How can a bridge be built between autonomic computing approaches and parallel computing systems? The work reported in this paper is motivated towards bridging this gap by proposing a swarm-array computing approach based on ���Intelligent Agents��� to achieve autonomy for distributed parallel computing systems. In the proposed approach, a task to be executed on parallel computing cores is carried onto a computing core by carrier agents that can seamlessly transfer between processing cores in the event of a predicted failure. The cognitive capabilities of the carrier agents on a parallel processing core serves in achieving the self-ware objectives of autonomic computing, hence applying autonomic computing concepts for the benefit of parallel computing systems. The feasibility of the proposed approach is validated by simulation studies using a multi-agent simulator on an FPGA (Field-Programmable Gate Array) and experimental studies using MPI (Message Passing Interface) on a computer cluster. Preliminary results confirm that applying autonomic computing principles to parallel computing systems is beneficial.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. �� 2005 IEEE.

Algoritmos de detec����o de bordas implementados em FPGA

Coordena����o de Aperfei��oamento de Pessoal de N��vel Superior (CAPES)

Pr��-regulador retificador boost com controle digital por valores m��dios, para sistema de ilumina����o fluorescente multi-l��mpadas, utilizando dispositivo FPGA e VHDL

Coordena����o de Aperfei��oamento de Pessoal de N��vel Superior (CAPES)

Controle digital atrav��s de dispositivo FPGA aplicado a um retificador trif��sico h��brido operando com modula����o por histerese vari��vel

Conselho Nacional de Desenvolvimento Cient��fico e Tecnol��gico (CNPq)

Ottimizzazione di protocolli di trasmissione dati tramite interfaccia usb implementati su fpga

La maggior parte dei moderni dispositivi e macchinari, sia ad uso civile che industriale, utilizzano sistemi elettronici che ne supervisionano e ne controllano il funzionamento. All��� interno di questi apparati �� quasi certamente impiegato un sistema di controllo digitale che svolge, anche grazie alle potenzialit�� oggi raggiunte, compiti che fino a non troppi anni or sono erano dominio dell��� elettronica analogica, si pensi ad esempio ai DSP (Digital Signal Processor) oggi impiegati nei sistemi di telecomunicazione. Nonostante l'elevata potenza di calcolo raggiunta dagli odierni microprocessori/microcontrollori/DSP dedicati alle applicazioni embedded, quando �� necessario eseguire elaborazioni complesse, time-critical, dovendo razionalizzare e ottimizzare le risorse a disposizione, come ad esempio spazio consumo e costi, la scelta ricade inevitabilmente sui dispositivi FPGA. I dispositivi FPGA, acronimo di Field Programmable Gate Array, sono circuiti integrati a larga scala d���integrazione (VLSI, Very Large Scale of Integration) che possono essere configurati via software dopo la produzione. Si differenziano dai microprocessori poich�� essi non eseguono un software, scritto ad esempio in linguaggio assembly oppure in linguaggio C. Sono invece dotati di risorse hardware generiche e configurabili (denominate Configurable Logic Block oppure Logic Array Block, a seconda del produttore del dispositivo) che per mezzo di un opportuno linguaggio, detto di descrizione hardware (HDL, Hardware Description Language) vengono interconnesse in modo da costituire circuiti logici digitali. In questo modo, �� possibile far assumere a questi dispositivi funzionalit�� logiche qualsiasi, non previste in origine dal progettista del circuito integrato ma realizzabili grazie alle strutture programmabili in esso presenti.

Implementing fully homomorphic encryption schemes in FPGA-based systems

LLas nuevas tecnolog��as orientadas a la nube, el internet de las cosas o las tendencias "as a service" se basan en el almacenamiento y procesamiento de datos en servidores remotos. Para garantizar la seguridad en la comunicaci��n de dichos datos al servidor remoto, y en el manejo de los mismos en dicho servidor, se hace uso de diferentes esquemas criptogr��ficos. Tradicionalmente, dichos sistemas criptogr��ficos se centran en encriptar los datos mientras no sea necesario procesarlos (es decir, durante la comunicaci��n y almacenamiento de los mismos). Sin embargo, una vez es necesario procesar dichos datos encriptados (en el servidor remoto), es necesario desencriptarlos, momento en el cual un intruso en dicho servidor podr��a a acceder a datos sensibles de usuarios del mismo. Es m��s, este enfoque tradicional necesita que el servidor sea capaz de desencriptar dichos datos, teniendo que confiar en la integridad de dicho servidor de no comprometer los datos. Como posible soluci��n a estos problemas, surgen los esquemas de encriptaci��n homom��rficos completos. Un esquema homom��rfico completo no requiere desencriptar los datos para operar con ellos, sino que es capaz de realizar las operaciones sobre los datos encriptados, manteniendo un homomorfismo entre el mensaje cifrado y el mensaje plano. De esta manera, cualquier intruso en el sistema no podr��a robar m��s que textos cifrados, siendo imposible un robo de los datos sensibles sin un robo de las claves de cifrado. Sin embargo, los esquemas de encriptaci��n homom��rfica son, actualmente, dr��s-ticamente lentos comparados con otros esquemas de encriptaci��n cl��sicos. Una op��eraci��n en el anillo del texto plano puede conllevar numerosas operaciones en el anillo del texto encriptado. Por esta raz��n, est��n surgiendo distintos planteamientos sobre como acelerar estos esquemas para un uso pr��ctico. Una de las propuestas para acelerar los esquemas homom��rficos consiste en el uso de High-Performance Computing (HPC) usando FPGAs (Field Programmable Gate Arrays). Una FPGA es un dispositivo semiconductor que contiene bloques de l��gica cuya interconexi��n y funcionalidad puede ser reprogramada. Al compilar para FPGAs, se genera un circuito hardware espec��fico para el algorithmo proporcionado, en lugar de hacer uso de instrucciones en una m��quina universal, lo que supone una gran ventaja con respecto a CPUs. Las FPGAs tienen, por tanto, claras difrencias con respecto a CPUs: -Arquitectura en pipeline: permite la obtenci��n de outputs sucesivos en tiempo constante -Posibilidad de tener multiples pipes para computaci��n concurrente/paralela. As��, en este proyecto: -Se realizan diferentes implementaciones de esquemas homom��rficos en sistemas basados en FPGAs. -Se analizan y estudian las ventajas y desventajas de los esquemas criptogr��ficos en sistemas basados en FPGAs, comparando con proyectos relacionados. -Se comparan las implementaciones con trabajos relacionados New cloud-based technologies, the internet of things or "as a service" trends are based in data storage and processing in a remote server. In order to guarantee a secure communication and handling of data, cryptographic schemes are used. Tradi��tionally, these cryptographic schemes focus on guaranteeing the security of data while storing and transferring it, not while operating with it. Therefore, once the server has to operate with that encrypted data, it first decrypts it, exposing unencrypted data to intruders in the server. Moreover, the whole traditional scheme is based on the assumption the server is reliable, giving it enough credentials to decipher data to process it. As a possible solution for this issues, fully homomorphic encryption(FHE) schemes is introduced. A fully homomorphic scheme does not require data decryption to operate, but rather operates over the cyphertext ring, keeping an homomorphism between the cyphertext ring and the plaintext ring. As a result, an outsider could only obtain encrypted data, making it impossible to retrieve the actual sensitive data without its associated cypher keys. However, using homomorphic encryption(HE) schemes impacts performance dras-tically, slowing it down. One operation in the plaintext space can lead to several operations in the cyphertext space. Because of this, different approaches address the problem of speeding up these schemes in order to become practical. One of these approaches consists in the use of High-Performance Computing (HPC) using FPGAs (Field Programmable Gate Array). An FPGA is an integrated circuit designed to be configured by a customer or a designer after manufacturing - hence "field-programmable". Compiling into FPGA means generating a circuit (hardware) specific for that algorithm, instead of having an universal machine and generating a set of machine instructions. FPGAs have, thus, clear differences compared to CPUs: - Pipeline architecture, which allows obtaining successive outputs in constant time. -Possibility of having multiple pipes for concurrent/parallel computation. Thereby, In this project: -We present different implementations of FHE schemes in FPGA-based systems. -We analyse and study advantages and drawbacks of the implemented FHE schemes, compared to related work.

Implementa����o em FPGA de m��dulo de efeito de reverbera����o

Reverberation is caused by the reflection of the sound in adjacent surfaces close to the sound source during its propagation to the listener. The impulsive response of an environment represents its reverberation characteristics. Being dependent on the environment, reverberation takes to the listener characteristics of the space where the sound is originated and its absence does not commonly sounds like ���natural���. When recording sounds, it is not always possible to have the desirable characteristics of reverberation of an environment, therefore methods for artificial reverberation have been developed, always seeking a more efficient implementations and more faithful to the real environments. This work presents an implementation in FPGAs (Field Programmable Gate Arrays ) of a classic digital reverberation audio structure, based on a proposal of Manfred Schroeder, using sets of all-pass and comb filters. The developed system exploits the use of reconfigurable hardware as a platform development and implementation of digital audio effects, focusing on the modularity and reuse characteristics

Impl��mentation sur FPGA de l���algorithme MUSIC sur antenne-r��seau exp��rimentale �� 10 GHz

Les techniques des directions d���arriv��e (DOA) sont une voie prometteuse pour accroitre la capacit�� des syst��mes et les services de t��l��communications en permettant de mieux estimer le canal radio-mobile. Elles permettent aussi de suivre pr��cis��ment des usagers cellulaires pour orienter les faisceaux d���antennes dans leur direction. S���inscrivant dans ce contexte, ce pr��sent m��moire d��crit ��tape par ��tape l���impl��mentation de l���algorithme de haut niveau MUSIC (MUltiple SIgnal Classification) sur une plateforme FPGA afin de d��terminer en temps r��el l���angle d���arriv��e d���une ou des sources incidentes �� un r��seau d���antennes. Le concept du prototypage rapide des lois de commande (RCP) avec les outils de XilinxTM System generator (XSG) et du MBDK (Model Based Design Kit) de NutaqTM est le concept de d��veloppement utilis��. Ce concept se base sur une programmation de code haut niveau �� travers des mod��les, pour g��n��rer automatiquement un code de bas niveau. Une attention particuli��re est port��e sur la m��thode choisie pour r��soudre le probl��me de la d��composition en valeurs et vecteurs propres de la matrice complexe de covariance par l���algorithme de Jacobi. L���architecture mise en place impl��mentant cette derni��re dans le FPGA (Field Programmable Gate Array) est d��taill��e. Par ailleurs, il est prouv�� que MUSIC ne peut effectuer une estimation int��ressante de la position des sources sans une calibration pr��alable du r��seau d���antennes. Ainsi, la technique de calibration par matrice G utilis��e dans ce projet est pr��sent��e, en plus de son mod��le d���impl��mentation. Enfin, les r��sultats exp��rimentaux du syst��me mis �� l�����preuve dans un environnement r��el en pr��sence d���une source puis de deux sources fortement corr��l��es sont illustr��s et analys��s.

Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA

This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. �� 2014 Technical University of Munich (TUM).