Advanced DC link capacitor technology application for a stiff voltage-source inverter

Problem of DC link size in a stiff voltage-source inverter for electric drive is described in the paper. Advantages of advanced film capacitor technology over conventional one for DC link application are reviewed. Conventional DC link capacitor selection methods are questioned in view of advanced capacitor technology utilization in stiff voltage-source inverter. For capacitor selection maximum ripple rms current point is shown. DC link ripple current spectrum analysis under modern PWM techniques is presented. Some capacitor selection recommendations are given. The analysis has been aided greatly by computer modeling in PSpice. ©2005 IEEE.

Hydrogen sensor based on silicon carbide (SiC) MOS capacitor

Silicon carbide (SiC) based MOS capacitor devices are used for gas sensing in high temperature and chemically reactive environments. A SiC MOS capacitor structure used as hydrogen sensor is defined and simulated. The effects of hydrogen concentration, temperature and interface traps on C-V characteristics were analysed. A comparison between structures with different oxide layer types (SiO2, TiO2 and ZnO) and thicknesses (50..10nm) was conducted. The TiO2 based structure has better performance than the SiO2 and ZnO structures. Also, the performance of the SiC MOS capacitor increases at thinner oxide layers. © 2012 IEEE.

A high-performance Si-based MOS electrooptic phase modulator with a shunt-capacitor configuration

A novel Si-based metal-oxide-semiconductor (MOS) electrooptic phase modulator including two shunt oxide layer capacitors integrated on a silicon-on-insulator (SOI) waveguide is simulated and analyzed. The refractive index near the two gate oxide layers is modified by the free carrier dispersion effect induced by applying a positive bias on the electrodes. The theoretical calculation of free carrier distribution coupled with optical guided mode propagation characteristics has been carried out. The influence of the structure parameters such as the width and the doping level of the active region are analyzed. A half-wave voltage V-pi = 4 V is demonstrated with an 8-mm active region length and a 4-mu m width of an inner rib under an accumulation mode. When decreasing the inner rib width to 1 mu m, the phase modulation efficiency is even higher, and the rise and fall times reach 50 and 40 ps, respectively, with a 1.0 x 10(17) cm(-3) doping level in the active region.

On the design and simulation of high speed electro-optic modulator based on SOI waveguide MOS dual capacitor structure

zhangdi于2010-03-29批量导入

A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor (MOS) capacitor configuration integrated into silicon-on-insulator (SOI).Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure,which boosts the modulation efficiency compared with a single MOS capacitor.The simulation results demonstrate that the VπLπ product is 2.4V·cm.The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve,respectively,indicating a bandwidth of 8GHz.The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

Design and simulation of charge sensitive preamplifier with CMOS FET implemented as feedback capacitor C-fp

In this paper, to design a new preamplifier for optimum performances with charged-particle or heavy-ion detectors, the CMOS FET is implemented as a feedback capacitor C-fp, so that the entire system should be built only with MOSFET. This work is a revolution design because to realize an ASIC for a preamplifier circuit, the capacitor will also be included. We succeed after a simulation to maintain a rise time less than 3 ns, the output resistance less than 94 Omega and the linearity almost good.

POLYANILINE ELECTROLYTIC CAPACITOR

Aluminum solid electrolytic capacitors with polyaniline doped with inorganic and organic acids as counterelectrode were fabricated, their properties were studied.

Toward Self-Assembled Ferroelectric Random Access Memories: Hard-Wired Switching Capacitor Arrays with Almost Tb/in.2 Densities

We report on the successful fabrication of arrays of switchable nanocapacitors made by harnessing the self-assembly of materials. The structures are composed of arrays of 20-40 nm diameter Pt nanowires, spaced 50-100 nm apart, electrodeposited through nanoporous alumina onto a thin film lower electrode on a silicon wafer. A thin film ferroelectric (both barium titanate (BTO) and lead zirconium titanate (PZT)) has been deposited on top of the nanowire array, followed by the deposition of thin film upper electrodes. The PZT nanocapacitors exhibit hysteresis loops with substantial remnant polarizations, while although the switching performance was inferior, the low-field characteristics of the BTO nanocapacitors show dielectric behavior comparable to conventional thin film heterostructures. While registration is not sufficient for commercial RAM production, this is nevertheless an embryonic form of the highest density hard-wired FRAM capacitor array reported to date and compares favorably with atomic force microscopy read-write densities.

Thin film capacitor cut from single crystals using focused ion beam milling

The focused ion beam microscope (FIB) has been used to fabricate thin parallel-sided ferroelectric capacitors from single crystals of BaTiO3 and SrTiO3. A series of nano-sized capacitors ranging in thickness from similar to660 nm to similar to300 nm were made. Cross-sectional high resolution transmission electron microscopy (HRTEM) revealed that during capacitor fabrication, the FIB rendered around 20 nm of dielectric at the electrode-dielectric interface amorphous, associated with local gallium impregnation. Such a region would act electrically in series with the single crystal and would presumably have a considerable negative influence on the dielectric properties. However, thermal annealing prior to gold electrodes deposition was found to fully recover the single crystal capacitors and homogenise the gallium profile. The dielectric testing of the STO ultra-thin single crystal capacitors was performed yielding a room temperature dielectric constant of similar to300, as is the case in bulk. Therefore, there was no evidence of a collapse in dielectric constant associated with thin film dimensions.

Physicochemical Investigation of Adiponitrile-Based Electrolytes for Electrical Double Layer Capacitor