Polarization switching induced decrease of bulk resistivity in ferroelectric Pb(Zr0.45Ti0.55)O3 thin films and a method to improve their fatigue endurance

Significant reduction of the bulk resistivity in a ferroelectric Pb(Zr 0.45Ti0.55)O3 thin film is observed before the remnant polarization started to decrease noticeably at the onset of its fatigue switching process. It is associated with the increase of charge carriers within the central bulk region of the film. The decrease of bulk resistivity would result in the increase of Joule heating effect, improving the temperature of the thin film, which is evaluated by the heat conduction analysis. The Joule heating effect in turn accelerates the polarization reduction, i.e. fatigue. Enhancing the heat dissipation of a ferroelectric capacitor is shown to be able to improve the device's fatigue endurance effectively. © 2013 Chinese Physical Society and IOP Publishing Ltd.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.

Tailoring carbon nanostructure for high frequency supercapacitor operation

The possibility of enhancing the frequency performance of electrochemical capacitors by tailoring the nanostructure of the carbon electrode to increase electrolyte permeability is demonstrated. Highly porous, vertically oriented carbon electrodes which are in direct electrical contact with the metallic current collector are produced via MPECVD growth on metal foils. The resulting structure has a capacitance and frequency performance between that of an electrolytic capacitor and an electrochemical capacitor. Fully packaged devices are produced on Ni and Cu current collectors and performance compared to state-of-the-art electrochemical capacitors and electrolytic capacitors. The extension of capacitive behavior to the AC regime (100 Hz) opens up an avenue for a number of new applications where physical volume of the capacitor may be significantly reduced. © 2014 Pritesh Hiralal et al.

薄场铝栅CMOS技术-器件电参数分析及大生产的工艺控制

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

A low-cost CMOS programmable temperature

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature T-th can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature T-th variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 mu m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature T(th)s from 45-120 degrees C with a 5 degrees C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm(2) and power consumption is 3.1 mu A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

An ultra-low power CMOS random number generator

This paper proposes an ultra-low power CMOS random number generator (RING), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 mu m CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 mu W. This novel circuit is a promising unit for low power system and communication applications. (c) 2007 Elsevier Ltd. All rights reserved.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation

The interface dipole and its role in the effective work function (EWF) modulation by Al incorporation are investigated. Our study shows that the interface dipole located at the high-k/SiO2 interface causes an electrostatic potential difference across the metal/high-k interface, which significantly shifts the band alignment between the metal and high-k, consequently modulating the EWF. The electrochemical potential equalization and electrostatic potential methods are used to evaluate the interface dipole and its contribution. The calculated EWF modulation agrees with experimental data and can provide insight to the control of EWF in future pMOS technology.

Enhanced charge storage characteristics of silicon nanocrystals fabricated by electron-beam coevaporation of Si and SiOx(x=1 or 2)

In this article, a simple and flexible electron-beam coevaporation (EBCE) technique has been reported of fabrication of the silicon nanocrystals (Si NCs) and their application to the nonvolatile memory. For EBCE, the Si and SiOx(x=1 or 2) were used as source materials. Transmission electron microscopy images and Raman spectra measurement verified the formation of the Si NCs. The average size and area density of the Si NCs can be adjusted by increasing the Si:O weight ratio in source material, which has a great impact on the crystalline volume fraction of the deposited film and on the charge storage characteristics of the Si NCs. A memory window as large as 6.6 V under +/- 8 V sweep voltage was observed for the metal-oxide-semiconductor capacitor structure with the embedded Si NCs.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

Silicon-on-insulating multi-layers for total-dose irradiation hardness

Silicon-on-insulating multi-layer (SOIM) materials were fabricated by co-implantation of oxygen and nitrogen ions with different energies and doses. The multilayer microstructure was investigated by cross-sectional transmission electron microscopy. P-channel metal-oxide-semiconductor (PMOS) transistors and metal-semiconductor-insulator-semiconductor (MSIS) capacitors were produced by these materials. After the irradiated total dose reaches 3 x 10(5) rad (Si), the threshold voltage of the SOIM-based PMOS transistor only shifts 0.07 V, while thin silicon-on-insulating buried-oxide SIMOX-based PMOS transistors have a shift of 1.2V, where SIMOX represents the separated by implanted oxygen. The difference of capacitance of the SOIM-based MSIS capacitors before and after irradiation is less than that of the thin-box SIMOX-based MSIS capacitor. The results suggest that the SOIM materials have a more remarkable irradiation tolerance of total dose effect, compared to the thin-buried-oxide SIMOX materials.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

Heteroepitaxial growth of novel SOI material Si/gamma-Al2O3/Si

In this paper, we report the fabrication of Si-based double hetero-epitaxial SOI materials Si/gamma-Al2O3/Si. First, single crystalline gamma-Al2O3 (100) insulator films were grown epitaxially on Si(100) by LPCVD, and then, Si(100) epitaxial films were grown on gamma-Al2O3 (100)/Si(100) epi-substrates using a CVD method similar to silicon on sapphire (SOS) epitaxial growth. The Si/gamma-Al2O3 (100)/Si(100) SOI materials are characterized in detail by RHEED, XRD and AES techniques. The results demonstrate that the device-quality novel SOI materials Si/gamma-Al2O3 (100)/Si(100) has been fabricated successfully and can be used for application of MOS device.

Heteroepitaxial growth and annealing of gamma-Al2O3 thin films on silicon

The gamma-Al2O3 films were grown on Si (100) substrates using the sources of TMA (Al (CH3)(3)) and O-2 by very low-pressure chemical vapor deposition (VLP-CVD). It has been found that the gamma-Al2O3 film has a mirror-like surface and the RMS was about 2.5nm. And the orientation relationship was gamma-Al2O3(100)/Si(100). The thickness uniformity of gamma-Al2O3 films for 2-inch epi-wafer was less than 5%. The X-ray diffraction (XRD) and reflection high-energy electron diffraction (RHEED) results show that the crystalline quality of the film was improved after the film was annealed at 1000degreesC in O-2 atmosphere. The high-frequency C-V and leakage current of Al/gamma-Al2O3/Si capacitor were also measured to verify the annealing effect of the film. The results show that the dielectric constant increased from 4 to 7 and the breakdown voltage for 65-nm-thick gamma-Al2O3 film on silicon increases from 17V to 53V.

微电子与光电子集成技术

微电子技术与光电子技术紧密结合，相互渗透，必将推进信息技术及相关的高新技术进入新的发展阶段。本书共分为9章，从技术基础和实际应用的角度出发，着重对微电子与光电子集成技术相关的工艺基础、基本原理和关键集成技术进行了详细阐述，主要内容包括光发射器件、光电探测器、光波导器件、光电子专用集成电路、硅基光电子集成回路、甚短距离光传输技术以及微电子与光电子混合集成技术等。 微电子与光电子集成技术的实用化进程，必将为21世纪科学技术的发展作出重大贡献。然而，微电子与光电子集成技术是信息技术发展的一个崭新方向，虽然各项关键技术的发展取得了一定的进步，但还存在诸多难题需要进一步解决和完善。 本书主要为从事集成光电子和光通信等相关技术研究的科研人员提供参考。