Temperature dependence of the mid-infrared dielectric function of YBCO in the a-b plane: a re-evaluation

The a-b plane dielectric function (epsilon) of c-axis YBa2Cu3O7-delta thin films with T-c > 85 K was measured at lambda = 3.392 mum in the temperature range 85-300 It, using an attenuated total reflectance (ATR) technique based on the excitation of surface plasmons, The results show that \epsilon (r)\ decreases quasi-linearly with increasing temperature, while Ei is invariant to temperature within experimental uncertainties. Typical values are epsilon (ab) = -23 + 16.5i at similar to 295 R and epsilon (ab) = -27 + 15.5i at similar to 90 K. A generalised Drude analysis yields effective scattering rates (1/tau*) that increase with temperature from similar to 1500 to similar to 1900 cm(-1). The temperature dependent rates best fit an equation of the form 1/tau* = a + bT(alpha) with alpha = 1.46 +/- 0.40. The effective plasma frequencies of w(p)* similar to 18,500 cm(-1) are almost independent of temperature. The uniquely detailed temperature dependence of the results confirm and consolidate data obtained by other groups using normal reflectance methods, but contradict our previously published ATR measurements. Technical shortcomings in the earlier work are identified as the source of the discrepancy. (C) 2000 Elsevier Science B.V. All rights reserved.

Electroconvection in a homeotropic bent-rod nematic liquid crystal beyond the dielectric inversion frequency

We characterize the structural transitions in an initially homeotropic bent-rod nematic liquid crystal excited by ac fields of frequency f well above the dielectric inversion point f(i). From the measured principal dielectric constants and electrical conductivities of the compound, the Carr-Helfrich conduction regime is anticipated to extend into the sub-megahertz region. Periodic patterned states occur through secondary bifurcations from the Freedericksz distorted state. An anchoring transition between the bend Freedericksz (1317) and degenerate planar (DP) states is detected. The BF state is metastable well above the Freedericksz threshold and gives way to the DP state, which persists in the field-off condition for several hours. Numerous +1 and -1 umbilics form at the onset of BF distortion, the former being largely of the chiral type. They survive in the DP configuration as linear defects, nonsingular in the core. In the BF regime, not far from fi, periodic Williams-like domains form around the umbilics; they drift along the director easy axis right from their onset. With increasing f, the wave vector of the periodic domains switches from parallel to normal disposition with respect to the c vector. Well above fi, a broadband instability is found.

Drifting periodic structures in a degenerate-planar bent-rod nematic liquid crystal beyond the dielectric inversion frequency

We report on the electric-field-generated effects in the nematic phase of a twin mesogen formed of bent-core and calamitic units, aligned homeotropically in the initial ground state and examined beyond the dielectric inversion point. The bend-Freedericksz (BF) state occurring at the primary bifurcation and containing a network of umbilics is metastable; we focus here on the degenerate planar (DP) configuration that establishes itself at the expense of the BF state in the course of an anchoring transition. In the DP regime, normal rolls, broad domains, and chevrons (both defect-mediated and defect-free types) form at various linear defect-sites, in different regions of the frequency-voltage plane. A significant novel aspect common to all these patterned states is the sustained propagative instability, which does not seem explicable on the basis of known driving mechanisms.

Three-dimensional pattern formation, multiple homogeneous soft modes, and nonlinear dielectric electroconvection

Patterns forming spontaneously in extended, three-dimensional, dissipative systems are likely to excite several homogeneous soft modes (approximate to hydrodynamic modes) of the underlying physical system, much more than quasi-one- (1D) and two-dimensional (2D) patterns are. The reason is the lack of damping boundaries. This paper compares two analytic techniques to derive the pattern dynamics from hydrodynamics, which are usually equivalent but lead to different results when applied to multiple homogeneous soft modes. Dielectric electroconvection in nematic liquid crystals is introduced as a model for 3D pattern formation. The 3D pattern dynamics including soft modes are derived. For slabs of large but finite thickness the description is reduced further to a 2D one. It is argued that the range of validity of 2D descriptions is limited to a very small region above threshold. The transition from 2D to 3D pattern dynamics is discussed. Experimentally testable predictions for the stable range of ideal patterns and the electric Nusselt numbers are made. For most results analytic approximations in terms of material parameters are given. [S1063-651X(00)09512-X].

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

(Invited) Germanium on Sapphire Technology

Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.