838 resultados para high performance sport
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WO3 nanoplate arrays with (002) oriented facets grown on fluorine doped SnO2 (FTO) glass substrates are tailored by tuning the precursor solution via a facile hydrothermal method. A 2-step hydrothermal method leads to the preferential growth of WO3 film with enriched (002) facets, which exhibits extraordinary photoelectrochemical (PEC) performance with a remarkable photocurrent density of 3.7 mA cm–2 at 1.23 V vs. revisable hydrogen electrode (RHE) under AM 1.5 G illumination without the use of any cocatalyst, corresponding to ~93% of the theoretical photocurrent of WO3. Density functional theory (DFT) calculations together with experimental studies reveal that the enhanced photocatalytic activity and better photo-stability of the WO3 films are attributed to the synergistic effect of highly reactive (002) facet and nanoplate structure which facilitates the photo–induced charge carrier separation and suppresses the formation of peroxo-species. Without the use of oxygen evolution cocatalysts, the excellent PEC performance, demonstrated in this work, by simply tuning crystal facets and nanostructure of pristine WO3 films may open up new opportunities in designing high performance photoanodes for PEC water splitting.
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Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.
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Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in making crucial design decisions, we build linear regression models that relate Processor performance to micro-architecture parameters, using simulation based experiments. We obtain good approximate models using an iterative process in which Akaike's information criteria is used to extract a good linear model from a small set of simulations, and limited further simulation is guided by the model using D-optimal experimental designs. The iterative process is repeated until desired error bounds are achieved. We used this procedure to establish the relationship of the CPI performance response to 26 key micro-architectural parameters using a detailed cycle-by-cycle superscalar processor simulator The resulting models provide a significance ordering on all micro-architectural parameters and their interactions, and explain the performance variations of micro-architectural techniques.
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Digest caches have been proposed as an effective method tospeed up packet classification in network processors. In this paper, weshow that the presence of a large number of small flows and a few largeflows in the Internet has an adverse impact on the performance of thesedigest caches. In the Internet, a few large flows transfer a majority ofthe packets whereas the contribution of several small flows to the totalnumber of packets transferred is small. In such a scenario, the LRUcache replacement policy, which gives maximum priority to the mostrecently accessed digest, tends to evict digests belonging to the few largeflows. We propose a new cache management algorithm called SaturatingPriority (SP) which aims at improving the performance of digest cachesin network processors by exploiting the disparity between the number offlows and the number of packets transferred. Our experimental resultsdemonstrate that SP performs better than the widely used LRU cachereplacement policy in size constrained caches. Further, we characterizethe misses experienced by flow identifiers in digest caches.
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The paper presents an adaptive Fourier filtering technique and a relaying scheme based on a combination of a digital band-pass filter along with a three-sample algorithm, for applications in high-speed numerical distance protection. To enhance the performance of above-mentioned technique, a high-speed fault detector has been used. MATLAB based simulation studies show that the adaptive Fourier filtering technique provides fast tripping for near faults and security for farther faults. The digital relaying scheme based on a combination of digital band-pass filter along with three-sample data window algorithm also provides accurate and high-speed detection of faults. The paper also proposes a high performance 16-bit fixed point DSP (Texas Instruments TMS320LF2407A) processor based hardware scheme suitable for implementation of the above techniques. To evaluate the performance of the proposed relaying scheme under steady state and transient conditions, PC based menu driven relay test procedures are developed using National Instruments LabVIEW software. The test signals are generated in real time using LabVIEW compatible analog output modules. The results obtained from the simulation studies as well as hardware implementations are also presented.
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Data Prefetchers identify and make use of any regularity present in the history/training stream to predict future references and prefetch them into the cache. The training information used is typically the primary misses seen at a particular cache level, which is a filtered version of the accesses seen by the cache. In this work we demonstrate that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers. In addition to empirical evaluation, we use the information theoretic metric entropy, to quantify the regularity present in extended histories. Entropy measurements indicate that extended histories are more regular than the default primary miss only training stream. Entropy measurements also help corroborate our empirical findings. With extended histories, further benefits can be achieved by triggering prefetches during secondary misses also. In this paper we explore the design space of extended prefetch histories and alternative prefetch trigger points for delta correlation prefetchers. We observe that different prefetch schemes benefit to a different extent with extended histories and alternative trigger points. Also the best performing design point varies on a per-benchmark basis. To meet these requirements, we propose a simple adaptive scheme that identifies the best performing design point for a benchmark-prefetcher combination at runtime. In SPEC2000 benchmarks, using all the L2 accesses as history for prefetcher improves the performance in terms of both IPC and misses reduced over techniques that use only primary misses as history. The adaptive scheme improves the performance of CZone prefetcher over Baseline by 4.6% on an average. These performance gains are accompanied by a moderate reduction in the memory traffic requirements.
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Hafnium dioxide (HfO2) films, deposited using electron beam evaporation, are optimized for high performance back-gated graphene transistors. Bilayer graphene is identified on HfO2/Si substrate using optical microscope and subsequently confirmed with Raman spectroscopy. Back-gated graphene transistor, with 32 nm thick HfO2 gate dielectric, has been fabricated with very high transconductance value of 60 mu S. From the hysteresis of the current-voltage characteristics, we estimate the trap density in HfO2 to be in the mid 10(11)/cm(2) range, comparable to SiO2.
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The advent of a new class of high-mobility semiconducting polymers opens up a window to address fundamental issues in electrical transport mechanism such as transport between localized states versus extended state conduction. Here, we investigate the origin of the ultralow degree of disorder (E-a similar to 16 meV) and the ``bandlike'' negative temperature (T) coefficient of the field effect electron mobility: mu(e)(FET) (T) in a high performance (mu(e)(FET) > 2.5 cm(2) V-1 s(-1)) diketopyrrolopyrrole based semiconducting polymer. Models based on the framework of mobility edge with exponential density of states are invoked to explain the trends in transport. The temperature window over which the system demonstrates delocalized transport was tuned by a systematic introduction of disorder at the transport interface. Additionally, the Hall mobility (mu(e)(Hall)) extracted from Hall voltage measurements in these devices was found to be comparable to field effect mobility (mu(e)(FET)) in the high T bandlike regime. Comprehensive studies with different combinations of dielectrics and semiconductors demonstrate the effectiveness of rationale molecular design, which emphasizes uniform-energetic landscape and low reorganization energy.
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This paper reports on the synthesis of zinc oxide (ZnO) nanostructures and examines the performance of nanocomposite thin-film transistors (TFTs) fabricated using ZnO dispersed in both n- and p-type polymer host matrices. The ZnO nanostructures considered here comprise nanowires and tetrapods and were synthesized using vapor phase deposition techniques involving the carbothermal reduction of solid-phase zinc-containing compounds. Measurement results of nanocomposite TFTs based on dispersion of ZnO nanorods in an n-type organic semiconductor ([6, 6]-phenyl-C61-butyric acid methyl ester) show electron field-effect mobilities in the range 0.3-0.6 cm2V-1 s-1. representing an approximate enhancement by as much as a factor of 40 from the pristine state. The on/off current ratio of the nanocomposite TFTs approach 106 at saturation with off-currents on the order of 10 pA. The results presented here, although preliminary, show a highly promising enhancement for realization of high-performance solution-processable n-type organic TFTs. © 2008 IEEE.
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In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, double-sided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.
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This paper reviews advances in the technology of integrated semiconductor optical amplifier based photonic switch fabrics, with particular emphasis on their suitability for high performance network switches for use within a datacenter. The key requirements for large port count optical switch fabrics are addressed noting the need for switches with substantial port counts. The design options for a 16×16 port photonic switch fabric architecture are discussed and the choice of a Clos-tree design is described. The control strategy, based on arbitration and scheduling, for an integrated switch fabric is explained. The detailed design and fabrication of the switch is followed by experimental characterization, showing net optical gain and operation at 10 Gb/s with bit error rates lower than 10-9. Finally improvements to the switch are suggested, which should result in 100 Gb/s per port operation at energy efficiencies of 3 pJ/bit. © 2011 Optical Society of America.
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A novel ultra-lightweight three-dimensional (3-D) cathode system for lithium sulphur (Li-S) batteries has been synthesised by loading sulphur on to an interconnected 3-D network of few-layered graphene (FLG) via a sulphur solution infiltration method. A free-standing FLG monolithic network foam was formed as a negative of a Ni metallic foam template by CVD followed by etching away of Ni. The FLG foam offers excellent electrical conductivity, an appropriate hierarchical pore structure for containing the electro-active sulphur and facilitates rapid electron/ion transport. This cathode system does not require any additional binding agents, conductive additives or a separate metallic current collector thus decreasing the weight of the cathode by typically ∼20-30 wt%. A Li-S battery with the sulphur-FLG foam cathode shows good electrochemical stability and high rate discharge capacity retention for up to 400 discharge/charge cycles at a high current density of 3200 mA g(-1). Even after 400 cycles the capacity decay is only ∼0.064% per cycle relative to the early (e.g. the 5th cycle) discharge capacity, while yielding an average columbic efficiency of ∼96.2%. Our results indicate the potential suitability of graphene foam for efficient, ultra-light and high-performance batteries.
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Under a high-pressure mercury lamp (HPML) and using an exposure time of 4 h, the photoproduction of hydroxyl radicals ((OH)-O-.) could be induced in an aqueous solution containing humic acid (HA). Hydroxyl radicals were determined by high-performance liquid chromatography using benzene as a probe. The results showed that (OH)-O-. photoproduction increased from 1.80 to 2.74 muM by increasing the HA concentration from 10 to 40 mg L-1 at an exposure time of 4 h (pH 6.5). Hydroxyl radical photoproduction in aqueous solutions of HA containing algae was greater than that in the aqueous solutions of HA without algae. The photoproduction of (OH)-O-. in the HA solution with Fe(111) was greater than that of the solution without Fe(III) at pH ranging from 4.0 to 8.0. The photoproduction of (OH)-O-. in HA solution with algae with or without Fe(111) under a 250 W HPML was greater than that under a 125 W HPML. The photoproduction of (OH)-O-. in irradiated samples was influenced by the pH. The results showed that HPML exposure for 4 h in the 4-8 pH range led to the highest (OH)-O-. photoproduction at pH 4.0.
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A Shubnikov-de Haas (SdH) oscillation measurement was performed on highly doped InAlAs/InGaAs metamorphic high-electron-mobility transistors on GaAs substrates at a temperature of 1.4 K. By analyzing the experimental data using fast Fourier transform, the electron densities and mobilities of more than one subband are obtained, and an obvious double-peak structure appears at high magnetic field in the Fourier spectrum. In comparing the results of SdH measurements, Hall measurements, and theoretical calculation, we found that this double-peak structure arises from spin splitting of the first-excited subband (i=1). Very close mobilities of 5859 and 5827 cm(2)/V s are deduced from this double-peak structure. The sum of the carrier concentration of all the subbands in the quantum well is only 3.95x10(12) cm(-2) due to incomplete transfer of the electrons from the Si delta -doped layer to the well. (C) 2001 American Institute of Physics.