Gigahertz multi-transistor graphene integrated circuits

We review the potential of graphene in ultra-high speed circuits. To date, most of high-frequency graphene circuits typically consist of a single transistor integrated with a few passive components. The development of multi-transistor graphene integrated circuits operating at GHz frequencies can pave the way for applications in which high operating speed is traded off against power consumption and circuit complexity. Novel vertical and planar devices based on a combination of graphene and layered materials could broaden the scope and performances of future devices. © 2013 IEEE.

Characterization and expression analysis of Paralichthys olivaceus voltage-dependent anion channel (VDAC) gene in response to virus infection

Voltage-dependent anion channel (VDAC, also known as mitochondrial porin) is acknowledged to play an important role in stress-induced mammalian apoptosis. In this study, Paralichthys olivaceus VDAC (PoVDAC) gene was identified as a virally induced gene from Scophthalmus Maximus Rhabdovirus (SMRV)-infected flounder embryonic cells (FEC). The full length of PoVDAC cDNA is 1380 bp with an open reading frame of 852 bp encoding a 283 amino acid protein. The deduced PoVDAC contains one alpha-helix, 13 transmembrane beta-strands and one eukaryotic mitochondrial porin signature motif. Constitutive expression of PoVDAC was confirmed in all tested tissues by real-time PCR. Further expression analysis revealed PoVDAC mRNA was upregulated by viral infection. We prepared fish antiserum against recombinant VDAC proteins and detected the PoVDAC in heart lysates from flounder as a 32 kDa band on western blot. Overexpression of PoVDAC in fish cells induced apoptosis. Immunofluoresence localization indicated that the significant distribution changes of PoVDAC have occurred in virus-induced apoptotic cells. This is the first report on the inductive expression of VDAC by viral infection, suggesting that PoVDAC might be mediated flounder antiviral immune response through induction of apoptosis. (c) 2007 Elsevier Ltd. All rights reserved.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10 6-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. © 2014 AIP Publishing LLC.

A Low-Voltage Silicon Light Emitting Device in Standard Salicide CMOS Technology

National Natural Science Foundation of China 60536030 60776024 60877035 90820002 National High-Technology Research and Development Program of China 2007AA04Z329 2007AA04Z254

Investigation of responsivity decreasing with rising bias voltage in a GaN Schottky barrier photodetector

The unexpected decrease in measured responsivity observed in a specific GaN Schottky barrier photodetector (PD) at high reverse bias voltage was investigated and explained. Device equivalent transforms and small signal analysis were performed to analyse the test circuit. On this basis, a model was built which explained the responsivity decrease quantitatively. After being revised by this model, responsivity curves varying with bias voltage turned out to be reasonable. It is proved that the decrease is related to the dynamic parallel resistance of the photodiode. The results indicate that with a GaN Schottky PD, the choice of load resistance is restricted according to the dynamic parallel resistance of the device to avoid responsivity decay at high bias voltage.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

Voltage tunable two-color InAs/GaAs quantum dot infrared photodetector

We report a bias voltage tunable two-color InAs/GaAs quantum dot infrared photodetector working under the normal incidence infared irradiation. The two-color detection of our device is realized by combining a photovoltaic and a photoconductive response by bias voltage tuning. The photovoltaic response is attributed to the transition of electron from the ground state to a high continuum state. The photoconductive response arises from the transition of electron from the ground state to the wetting layer state through the barrier via Fowler-Nordheim tunneling evidenced by a broad feature of the photocurrent peak on the high energy side. (C) 2008 American Institute of Physics.

Influence of spacer layer thickness on the current-voltage characteristics of pseudomorphic AlAs/In0.53Ga0.47As/InAs resonant tunnelling diodes

This paper investigates the dependence of current-voltage characteristics of AlAs/In0.53Ga0.47As/InAs resonant tunnelling diodes (RTDs) on spacer layer thickness. It finds that the peak and the valley current density J in the negative differential resistance (NDR) region depends strongly on the thickness of the spacer layer. The measured peak to valley current ratio of RTDs studied here is shown to improve while the current density through RTDs decreases with increasing spacer layer thickness below a critical value.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

Dielectric relaxation and giant dielectric constant of Nb-doped CaCu3Ti4O12 ceramics under dc bias voltage

CaCu3Ti(4-x)Nb(x)O(12) (x = 0, 0.01, 0.08, 0.2) ceramics were fabricated by a conventional solid-state reaction method. The ceramics showed the body-centered cubic structure without any foreign phases and the grain size decreases with Nb doping. Two Debye-type relaxations were observed for the Nb-doped samples at low frequency and high frequency, respectively. The complex electric modulus analysis revealed that the surface layer, grains and grain boundaries contributed to the dielectric constant. The low-frequency dielectric constant relative to the surface layer decreased to a minimum and then increased with the dc bias voltage at 100 Hz, which were well explained in terms of a model containing two metal oxide semiconductors in series, confirming the surface layer in the ceramics. The shift voltage V-B corresponding to the minimal capacitance increased with increase of the composition x. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of Anode Floating Voltage and its Applications in Characterizing Silicon Drift Detectors

Anode floating voltage is predicted and investigated for silicon drift detectors (SDDs) with an active area of 5 mm(2) fabricated by a double-side parallel technology. It is demonstrated that the anode floating voltage increases with the increasing inner ring voltage, and is almost unchanged with the external ring voltage. The anode floating voltage will not be affected by the back electrode biased voltage until it reaches the full-depleted voltage (-50 V) of the SDD. Theoretical analysis and experimental results show that the anode floating voltage is equal to the sum of the inner ring voltage and the built-in potential between the p(+) inner ring and the n(+) anode. A fast checking method before detector encapsulation is proposed by employing the anode floating voltage along with checking the leakage current, potential distribution and drift properties.

The junction temperature and forward voltage relationship of GaN-based laser diode

In GaAs-based light-emitting diode (LED) or laser diode (LD), the forward voltage (V) will decrease linearly with the increasing junction temperature (T). This can be used as a convenient method to measure the junction temperature. In GaN-based LED, the relationship is linear too. But in GaN-based LD, the acceptor M (g) in p-GaN material can not ionize completely at-room temperature, and the carrier density will change with temperature. But we find finally that, this change won't lead to a nonlinear relationship of V-T. Our experiments show that it is Linear too.