La crítica de Plotino a la concepción aristotélica del tiempo en "En". III 7

El presente trabajo intenta mostrar de qué manera Plotino refuta la noción aristotélica del tiempo como «número» o «medida del movimiento», cuáles son las aporías que plantea, cómo las compulsa con sus propios argumentos y qué soluciones propone con respecto a esa misma confrontación. Todo esto será encauzado a partir de un estudio descriptivo y analítico, acompañado de una lectura a la vez hermenéutica y crítica de los textos seleccionados para esta ocasión.

Full Irish: New Architecture in Ireland

Full Irish New Architecture in Ireland profiles 16 firms in the Republic of Ireland and Northern Ireland including photographs, drawings and text. Its publisher, Princeton Architectural Press, has won numerous international awards for highest quality academic and practice-based publications. The author was approached by the editors to write the book.

Art and Architecture of Ireland Volume Four:Architecture: 1600-2000

Three Entries: Peacelines; Public Housing in Northern Ireland in the Twentieth Century; Interpretive Centres, NI Peacelines, NI Social Housing

MSGR-based Low Latency Complex Matrix Inversion Architecture

This paper presents a matrix inversion architecture based on the novel Modified Squared Givens Rotations (MSGR) algorithm, which extends the original SGR method to complex valued data, and also corrects erroneous results in the original SGR method when zeros occur on the diagonal of the matrix either initially or during processing. The MSGR algorithm also avoids complex dividers in the matrix inversion, thus minimising the complexity of potential real-time implementations. A systolic array architecture is implemented and FPGA synthesis results indicate a high-throughput low-latency complex matrix inversion solution. © 2008 IEEE.

Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.