MSGR-based Low Latency Complex Matrix Inversion Architecture


Autoria(s): Ma, L.; Dickson, K.; Mcallister, J.; Mccanny, J.
Data(s)

01/10/2008

Identificador

http://pure.qub.ac.uk/portal/en/publications/msgrbased-low-latency-complex-matrix-inversion-architecture(1397e40e-ef97-42e2-906c-c9afe8d3acf4).html

http://dx.doi.org/10.1109/ICOSP.2008.4697158

http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-67249157964&md5=af33776025d0649a4bae7a208e4856c3

Idioma(s)

eng

Direitos

info:eu-repo/semantics/restrictedAccess

Fonte

Ma , L , Dickson , K , Mcallister , J & Mccanny , J 2008 , MSGR-based Low Latency Complex Matrix Inversion Architecture . in International Conference on Signal Processing Proceedings, ICSP . pp. 410-413 . DOI: 10.1109/ICOSP.2008.4697158

Tipo

contributionToPeriodical

Resumo

This paper presents a matrix inversion architecture based on the novel Modified Squared Givens Rotations (MSGR) algorithm, which extends the original SGR method to complex valued data, and also corrects erroneous results in the original SGR method when zeros occur on the diagonal of the matrix either initially or during processing. The MSGR algorithm also avoids complex dividers in the matrix inversion, thus minimising the complexity of potential real-time implementations. A systolic array architecture is implemented and FPGA synthesis results indicate a high-throughput low-latency complex matrix inversion solution. © 2008 IEEE.

Palavras-Chave #/dk/atira/pure/subjectarea/asjc/1700/1706 #Computer Science Applications #/dk/atira/pure/subjectarea/asjc/1700/1711 #Signal Processing #/dk/atira/pure/subjectarea/asjc/1700/1712 #Software