A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Simple method for estimating minimum bend radii of SOI single mode curved rib waveguides

A simple method based on the effective index method was used to estimate the minimum bend radii of curved SOI waveguides. An analytical formula was obtained to estimate the minimum radius of curvature at which the mode becomes cut off due to the side radiative loss.

Carrier capture into InAs/GaAs quantum dots detected by a simple degenerate pump-probe technique

We demonstrate that the carrier capture and relaxation processes in InAs/GaAs quantum dots can be detected by a simple degenerate pump-probe technique. We have observed a rising process in the transient reflectivity, following the initial fast relaxation in a GaAs matrix, and assigned this rising process to the carrier capture from the GaAs barriers to the InAs layers. The assignment was modeled using the Kramers-Kronig relations. The capture time was found to depend strongly on the InAs layer thickness as well as on the excitation density and photon energy. (C) 2000 Elsevier Science Ltd. All rights reserved.

Simple reflection technique for measuring the linear electro-optic coefficient of the polymer thin films

The simple reflection technique is usually used to measure the linear electro-optic (EO) coefficient (Pockels coefficient) in the development of EO polymer thin films. But there are some problems in some articles in the determination of the phase shift between the s and p light modes of a laser beam waveguided into the polymer film while a modulating voltage is applied across the electrodes, and different expressions for the linear EO coefficient measured have been given in these articles. In our research, more accurate expression of the linear EO coefficient was deduced by suitable considering the phase shift between the s and p light modes. The linear EO coefficients of several polymer thin films were measured by reflection technique, and the results of the Linear EO coefficient calculated by different expressions were compared. The limit of the simple reflection technique for measuring the linear EO coefficient of the polymer thin films was discussed.

Ground-state properties of an artificial molecule: a simple model calculation for the double quantum dot

The ground state of a double quantum-dot structure is studied by a simplified Anderson-type model. Numerical calculations reveal that the ground-state level of this artificial molecule increases with the increasing single particle level of the dot, and also increases with the decreasing transfer integrals. We show the staircase feature of the electron occupation and the properties of the ground-state eigenvector by varying the;single particle level of the dot.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A simple method to realize large-bandwidth and high-efficiency wavelength conversion in Si waveguide

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-06-04T07:06:36Z No. of bitstreams: 1 A simple method to realize large-bandwidth and high-efficiency wavelength conversion in Si waveguide.pdf: 277035 bytes, checksum: ca7e272b2286b305d385825417857f21 (MD5)

a simple but effective improvement to the plumb-line algorithm

Emporiki Bank; Microsoft; Alpha Bank

Experimental study on flow characters of CH3CCl2F hydrate slurry

The flow behaviors of CH3CCl2F hydrate slurry with volume concentration of 10-70% were studied in a new built flow loop with a diameter of 42.0 mm and length of 30.0 m. Morphologies of the fluids from slurrylike hydrates to slushlike hydrates with increasing of hydrate volume concentration in pipeline were observed. Pressure drops in pipeline also were studied and an exceptional pressure transition zone with hydrate volume concentration between 30% and 40% was found for the first time, which can be used as a notation to judge if the pipeline runs safely or not. Fanning friction factors of the hydrate slurries with all hydrate contents tend to constants between 0.38 and 0.5, which depend on the volume concentration in slurries, when the velocity reaches 1.5 m/s. A simple relation to estimate the pressure drop of hydrate slurry in pipeline was presented and verified. Experimental results were compared to the estimated results, which showed a good agreement. 

Spectrum shape compression and pedestal elimination employing a Sagnac loop

We report on the experimental demonstration of a spectrum shaping filter, which is formed by inserting a fiber polarization controller (PC) in to a Sagnac loop. Pedestal free and narrow spectrum with line width at 1.4-1.7 nm is obtained, which is advantageous for further power amplification and effective frequency doubling. (C) 2008 Elsevier B.V. All rights reserved.