A versatile content addressable memory architecture

In this paper, a novel configurable content addressable memory (CCAM) cell is proposed, to increase the flexibility of embedded CAMs for SoC employment. It can be easily configured as a Binary CAM (BiCAM) or Ternary CAM (TCAM) without significant penalty of power consumption or searching speed. A 64x128 CCAM array has been built and verified through simulation. ©2007 IEEE.

High performance IP lookup circuit using DDR SDRAM

DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10Gbps, providing a solution on high-performance and economic packet header inspections. ©2008 IEEE.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

Does flexibility in secondary level mathematics curriculum affect degree performance?

The authors have much experience in developing mathematics skills of first-year engineering students and attempting to ensure a smooth transition from secondary school to university. Concerns exist due to there being flexibility in the choice of modules needed to obtain a secondary level (A-level) mathematics qualification. This qualification is based on some core (pure maths) modules and a selection from mechanics and statistics modules. A survey of aerospace and mechanical engineering students in Queen’s University Belfast revealed that a combination of both mechanics and statistics (the basic module in both) was by far the most popular choice and therefore only about one quarter of this cohort had studied mechanics beyond the basic module within school maths. Those students who studied the extra mechanics and who achieved top grades at school subsequently did better in two core, first-year engineering courses. However, students with a lower grade from school did not seem to gain any significant advantage in the first-year engineering courses despite having the extra mechanics background. This investigation ties in with ongoing and wider concerns with secondary level mathematics provision in the UK.

The adsorption, storage and release of nitric oxide using ion exchanged zeolites

Zeolites exchanged with transition metal cations Co2+, Mn2+, Zn2+ and Cu2+ are capable of storing and delivering a large quantity of nitric oxide in a range of 1.2-2.7 mmolg(-1). The metal ion exchange impacts the pore volumes of zeolite FAU more significantly than LTA. The storage of NO mainly involves coordination of NO to metal cation sites. By exposing zeolites to a moisture atmosphere, the stored nitric oxide can be released. The NO release takes more than 2 hours for the NO concentration decreasing below similar to 5ppb in outlet gas. Its release rate can be controlled by tailoring zeolite frameworks and optimising release conditions.

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.

Prefetching and Cache Management using Task Lifetimes

Task-based dataflow programming models and runtimes emerge as promising candidates for programming multicore and manycore architectures. These programming models analyze dynamically task dependencies at runtime and schedule independent tasks concurrently to the processing elements. In such models, cache locality, which is critical for performance, becomes more challenging in the presence of fine-grain tasks, and in architectures with many simple cores.

This paper presents a combined hardware-software approach to improve cache locality and offer better performance is terms of execution time and energy in the memory system. We propose the explicit bulk prefetcher (EBP) and epoch-based cache management (ECM) to help runtimes prefetch task data and guide the replacement decisions in caches. The runtimem software can use this hardware support to expose its internal knowledge about the tasks to the architecture and achieve more efficient task-based execution. Our combined scheme outperforms HW-only prefetchers and state-of-the-art replacement policies, improves performance by an average of 17%, generates on average 26% fewer L2 misses, and consumes on average 28% less energy in the components of the memory system.