Compact and efficient triple-pass optical parametric chirped pulse amplification

Compact and efficient triple-pass optical parametric chirped pulse amplification in a single crystal has been demonstrated. The signal was triple-pass amplified in a single nonlinear crystal by a nanosecond pump pulse. The first-pass optical parametric amplification is completely phase matched in the plane of the maximum effective nonlinearity, and the other two passes work symmetrically near to the first-pass optical parametric amplification plane. This architecture efficiently increases the overall gain, overcomes the optical parametric fluorescence, and clearly simplifies the amplification scheme.

Thermal analysis and test for single concentrator solar cells

A thermal model for concentrator solar cells based on energy conservation principles was designed. Under 400X concentration with no cooling aid, the cell temperature would get up to about 1200℃.Metal plates were used as heat sinks for cooling the system, which remarkably reduce the cell temperature. For a fixed concentration ratio, the cell temperature reduced as the heat sink area increased. In order to keep the cell at a constant temperature, the heat sink area needs to increase linearly as a function of the concentration ratio. GaInP/GaAs/Ge triple-junction solar cells were fabricated to verify the model. A cell temperature of 37℃ was measured when using a heat sink at 400X concentratration.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

A Radial Stub Test Circuit for Microwave Power Devices

With the principles of microwave circuits and semiconductor device physics, two microwave power device test circuits combined with a test fixture are designed and simulated, whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz. The simulation and experimental results verify that the test circuit with a radial stub is better than that without. As an example, a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture. With a 5.4GHz microwave input signal, the maximum gain is 8.75dB, and the maximum output power is 33.2dBm.

Two-port calibration of test fixtures with OSL method.

The open-short-load (OSL) method is very simple and widely used, for one-port test fixture calibration. In this paper, this method. is extended to the two-port calibration of test fixtures for the first time. The problem of phase uncertainty arising in this application has been solved. The comparison between our results and those obtained with the short-open-load-thru (SOLT) method shows that the method established is accurate enough for practical applications.

Frequency limitation in calibrating microwave test fixtures

The problem of frequency limitation arising in calibration of the test fixtures is investigated in this paper. It is found that at some frequencies periodically, the accuracy of the methods becomes very low, and. the denominators of the expressions of the required S-parameters approach zero. This conclusion can be drawn whether-the test fixtures, are symmetric or not. A good agreement between theory and experiment is obtained.

Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.