924 resultados para Specification


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Leadership and Management Standards in the UK Lifelong Learning Sector. Presentation on research findings on leadership and management in the LLS sector, in the context of UK government policy changes introducing the 2007 Principals' Qualifying Programme (PQP) delivered by the Centre for Excellence in Leadership (CEL)/Learning and Skills Improvement Service (LSIS). Discusses the role of standards in leadership and management professional practice and development and sums up the history of development of standards in relation to the National Occupational Standards (NOS) for Leadership and Management, based on the UK Management Standards Centre (MSC) Institute for Leadership and Management Standards. Discusses the Lifelong Learning UK (LLUK) Benchmark Role Specification for Principals in FE, Sixth Form and Specialist Colleges and the fact that the LSIS PQP has adopted those as part of its programme for Principal development. In the context of the implementation of standards for leadership and management, discusses the importance of values-based and research-informed leadership and the development of trust in lifelong learning sector institutions, given the multiple challenges facing vocational education and training (VET) institutions and the relative lack of recognition and support for the difficult roles taken on by Principals and senior leaders.

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Görzig, H., Engel, F., Brocks, H., Vogel, T. & Hemmje, M. (2015, August). Towards Data Management Planning Support for Research Data. Paper presented at the ASE International Conference on Data Science, Stanford, United States of America.

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In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

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This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

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We report findings from a choice experiment survey designed to estimate the economic benefits of policy measures to improve the rural landscape in the Republic of Ireland. Using a panel mixed logit specification to account for unobserved taste heterogeneity we derived individual-specific willingness-to-pay (WTP) estimates for each respondent in the sample. We subsequently investigated the spatial dependence of these estimates. Results suggest the existence of positive spatial autocorrelation for all rural landscape attributes. As a means of benefit transfer, kriging methods were employed to interpolate WTP estimates across the whole of the Republic of Ireland. The kriged WTP surfaces confirm the existence of spatial dependence and illustrate the implied spatial variation and regional disparities in WTP for all the rural landscape improvements investigated.

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Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50 duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100 but power output capability is less than that the 50 duty ratio case would permit. To facilitate comparison between 50 (optimal) and non-50 (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50 suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. © The Institution of Engineering and Technology 2007.

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In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

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A power combining strategy for Class-E and inverse Class-E amplifiers operating at high frequencies such that they can operate into unbalanced loads is proposed. This power combining method is particularly important for the inverse Class-E amplifier configuration whose single-stage topology is naturally limited for small-to-medium power applications. Design examples for the power combining synthesis of classical Class-E and then inverse Class-E amplifiers with specification 3 V-1.5 W-2.5 GHz are given. For this specification, it is shown that a three-branch combiner has a natural 50 V output impedance. The resulting circuits are simulated within Agilent Advanced Design Systems environment with good agreement to theoretical prediction. Further the performance of the proposed circuits when operated in a Linear amplification using Nonlinear Components transmitter configuration whereby two-branch amplifiers are driven with constant amplitude conjugate input phase signals is investigated.

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Social exclusion and social capital are widely used concepts with multiple and ambiguous definitions. Their meanings and indicators partially overlap, and thus they are sometimes used interchangeably to refer to the inter-relations of economy and society. Both ideas could benefit from further specification and differentiation. The causes of social exclusion and the consequences of social capital have received the fullest elaboration, to the relative neglect of the outcomes of social exclusion and the genesis of social capital. This article identifies the similarities and differences between social exclusion and social capital. We compare the intellectual histories and theoretical orientations of each term, their empirical manifestations and their place in public policy. The article then moves on to elucidate further each set of ideas. A central argument is that the conflation of these notions partly emerges from a shared theoretical tradition, but also from insufficient theorizing of the processes in which each phenomenon is implicated. A number of suggestions are made for sharpening their explanatory focus, in particular better differentiating between cause and consequence, contextualizing social relations and social networks, and subjecting the policy 'solutions' that follow from each perspective to critical scrutiny. Placing the two in dialogue is beneficial for the further development of each.

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Background: Glycogen synthase kinase-3 (GSK-8) is a serine/threonine protein kinase, the activity of which is inhibited by a variety of extracellular stimuli including insulin, growth factors, cell specification factors and cell adhesion. Consequently, inhibition of GSK-3 activity has been proposed to play a role in the regulation of numerous signalling pathways that elicit pleiotropic cellular responses. This report describes the identification and characterisation of potent and selective small molecule inhibitors of GSK-3.

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Durability of concrete is a great concern to all designers, owners and users of reinforced concrete structures. As a result, more restrictive regulations are being introduced in various Codes of Practice dealing with the design of these structures. Attempts are being made by various researchers to develop performance based specification. For this to be successful standard non destructive tests are required which will be used to assess the durability of concretes. In parallel with this approach, a research team in Queen’s University Belfast, U. K., investigated the effect of different mix parameters on workability, strength and various permeation properties. Furthermore, durability parameters such as freeze-thaw salt scaling resistance and carbonation depth were also investigated. The research was part funded by the Department of Environment, Transport and the Regions (DETR). This paper reports of the findings from this study. The results from this investigation showed that some of the non destructive tests used were reasonably well correlated with carbonation and freeze-thaw salt scaling resistance of CEM I concrete. If the mix parameters such as aggregate-cement ratio or water-cement ratio are known, better correlation can be obtained. Further investigation is required varying other mix parameters including various aggregates, admixtures and air entrainments before the result can be used for developing mix design methods for durable concretes. Also long term site tests are required to validate the results obtained from the accelerated laboratory tests used to study the carbonation resistance and freeze-thaw salt scaling resistance.

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Developing a desirable framework for handling inconsistencies in software requirements specifications is a challenging problem. It has been widely recognized that the relative priority of requirements can help developers to make some necessary trade-off decisions for resolving con- flicts. However, for most distributed development such as viewpoints-based approaches, different stakeholders may assign different levels of priority to the same shared requirements statement from their own perspectives. The disagreement in the local levels of priority assigned to the same shared requirements statement often puts developers into a dilemma during the inconsistency handling process. The main contribution of this paper is to present a prioritized merging-based framework for handling inconsistency in distributed software requirements specifications. Given a set of distributed inconsistent requirements collections with the local prioritization, we first construct a requirements specification with a prioritization from an overall perspective. We provide two approaches to constructing a requirements specification with the global prioritization, including a merging-based construction and a priority vector-based construction. Following this, we derive proposals for handling inconsistencies from the globally prioritized requirements specification in terms of prioritized merging. Moreover, from the overall perspective, these proposals may be viewed as the most appropriate to modifying the given inconsistent requirements specification in the sense of the ordering relation over all the consistent subsets of the requirements specification. Finally, we consider applying negotiation-based techniques to viewpoints so as to identify an acceptable common proposal from these proposals.

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Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

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For any proposed software project, when the software requirements specification has been established, requirements changes may result in not only a modification of the requirements specification but also a series of modifications of all existing artifacts during the development. Then it is necessary to provide effective and flexible requirements changes management. In this paper, we present an approach to managing requirements changes based on Booth’s negotiation-style framework for belief revision. Informally, we consider the current requirements specification as a belief set about the system-to-be. The request of requirements change is viewed as new information about the same system-to-be. Then the process of executing the requirements change is a process of revising beliefs about the system-to-be. We design a family of belief negotiation models appropriate for different processes of requirements revision, including the setting of the request of requirements change being fully accepted, the setting of the current requirements specification being fully preserved, and that of the current specification and the request of requirements change reaching a compromise. In particular, the prioritization of requirements plays an important role in reaching an agreement in each belief negotiation model designed in this paper.

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Purpose: The issue of accounting change, why and how accounting evolves through time and within specific organisational settings, has been addressed by an important body of literature. This paper aims to explain why, in processes of accounting change, organisations confronting similar environmental pressures show different outcomes of change.

Design/methodology/approach: Drawing on archetype theory, the paper analyses the case of two Italian local governments. Comparative case studies were carried out, reconstructing a period of 15 years.

Findings: Although confronted with similar environmental pressures, the two cases show two different patterns of accounting change, where only one case is able to finally reach radical change. Accounting change can be prompted by external stimuli, but, once the change is prompted, the outcomes of the change are explained by the dynamics of intra-organisational conditions.

Originality/value: The study contributes to accounting change literature by adopting an approach (i.e. archetype theory) that overcomes some of the limitations of previous studies in explaining variations in organisational change. Through this, the authors are able to explain different outcomes and paces of accounting change and point out the intra-organisational factors also affecting them in the presence of similar environmental pressures. A specification of the theoretical framework in a particular setting is also provided.