Towards high performance and multi-functional structural membranes using advanced fibrous and textile materials

Scientific and technological advancements in the area of fibrous and textile materials have greatly enhanced their application potential in several high-end technical and industrial sectors including construction, transportation, medical, sports, aerospace engineering, electronics and so on. Excellent performance accompanied by light-weight, mechanical flexibility, tailor-ability, design flexibility, easy fabrication and relatively lower cost are the driving forces towards wide applications of these materials. Cost-effective fabrication of various advanced and functional materials for structural parts, medical devices, sensors, energy harvesting devices, capacitors, batteries, and many others has been possible using fibrous and textile materials. Structural membranes are one of the innovative applications of textile structures and these novel building skins are becoming very popular due to flexible design aesthetics, durability, lightweight and cost benefits. Current demand on high performance and multi-functional materials in structural applications has motivated to go beyond the basic textile structures used for structural membranes and to use innovative textile materials. Structural membranes with self-cleaning, thermoregulation and energy harvesting capability (using solar cells) are examples of such recently developed multi-functional membranes. Besides these, there exist enormous opportunities to develop wide varieties of multi-functional membranes using functional textile materials. Additionally, it is also possible to further enhance the performance and functionalities of structural membranes using advanced fibrous architectures such as 2D, 3D, hybrid, multi-layer and so on. In this context, the present paper gives an overview of various advanced and functional fibrous and textile materials which have enormous application potential in structural membranes.

Arquitecturas imaginárias. Espaço real e ilusório no Barroco português

Tese de Doutoramento em Arquitectura / Cultura Arquitectónica.

Prevalência e susceptibilidade de isolados clínicos de Pseudomonas aeruginosa numa unidade hospitalar de Portugal

Dissertação de mestrado em Bioquímica Aplicada (área de especialização em Biomedicina)

Desenvolvimento de um processador VLIW

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores

Development of advanced cell/tissue culture systems, based on enhanced polymeric scaffolds and sophisticated bioreactors, for tissue engineering applications

Programa Doutoral em Engenharia Biomédica

Hybrid hypervisor partially deployed on FPGA

Tese de Doutoramento em Engenharia Eletrónica e Computadores.

Towards an engine for coordination-based architectural reconfigurations

Software reconfigurability became increasingly relevant to the architectural process due to the crescent dependency of modern societies on reliable and adaptable systems. Such systems are supposed to adapt themselves to surrounding environmental changes with minimal service disruption, if any. This paper introduces an engine that statically applies reconfigurations to (formal) models of software architectures. Reconfigurations are specified using a domain specific language— ReCooPLa—which targets the manipulation of software coordinationstructures,typicallyusedinservice-orientedarchitectures(soa).Theengine is responsible for the compilation of ReCooPLa instances and their application to the relevant coordination structures. The resulting configurations are amenable to formal analysis of qualitative and quantitative (probabilistic) properties.

On the verification of architectural reconfigurations

In a reconfigurable system, the response to contextual or internal change may trigger reconfiguration events which, on their turn, activate scripts that change the system׳s architecture at runtime. To be safe, however, such reconfigurations are expected to obey the fundamental principles originally specified by its architect. This paper introduces an approach to ensure that such principles are observed along reconfigurations by verifying them against concrete specifications in a suitable logic. Architectures, reconfiguration scripts, and principles are specified in Archery, an architectural description language with formal semantics. Principles are encoded as constraints, which become formulas of a two-layer graded hybrid logic, where the upper layer restricts reconfigurations, and the lower layer constrains the resulting configurations. Constraints are verified by translating them into logic formulas, which are interpreted over models derived from Archery specifications of architectures and reconfigurations. Suitable notions of bisimulation and refinement, to which the architect may resort to compare configurations, are given, and their relationship with modal validity is discussed.

Extremely strong and tough hydrogels as prospective candidates for tissue repair – A review

Ideal candidates for the repair of robust biological tissues should exhibit diverse features such as biocompatibility, strength, toughness, self-healing ability and a well-defined structure. Among the available biomaterials, hydrogels, as highly hydrated 3D-crosslinked polymeric networks, are promising for Tissue Engineering purposes as result of their high resemblance with native extracellular matrix. However, these polymeric structures often exhibit a poor mechanical behavior, hampering their use in load-bearing applications. During the last years, several efforts have been made to create new strategies and concepts to fabricate strong and tough hydrogels. Although it is already possible to shape the mechanical properties of artificial hydrogels to mimic biotissues, critical issues regarding, for instance, their biocompatibility and hierarchical structure are often neglected. Therefore, this review covers the structural and mechanical characteristics of the developed methodologies to toughen hydrogels, highlighting some pioneering efforts employed to combine the aforementioned properties in natural-based hydrogels.

Participación de los glucocorticoides en las secuelas emocionales inducidas por estrés

El proyecto tiene como objetivo estudiar la implicancia funcional de los glucocorticoides liberados durante diferentes situaciones estresantes en las consecuencias comportamentales inducidas por las mismas. Asimismo, se evaluará la influencia de los esteroides en los cambios neuroquímicos (neurotransmisión gabaérgica) y neuroendócrinos (actividad del sistema hipotalámico-hipofisario-adrenal, HHA) que subyacen a las alteraciones comportamentales. El estudio contribuye, además, a la caracterización de los mecanismos neurales implicados en los déficits conductuales inducidos por estrés. Durante este período se abordarán los siguientes objetivos específicos: a) Caracterización de los sistemas de receptores centrales (MR o GR) involucrados en la respuesta ansiogénica inducida por una sesión de inmovilización y de las áreas centrales comprometidas. (...) De este modo se extenderán los hallazgos conductuales a la actividad del complejo supramolecular GABAa. b) Evaluación de los efectos inducidos por la inyección sistémica aguda de dexametasona sobre la funcionalidad complejo-receptor GABAa en corteza prefrontal por medio de la determinación de la captación de cloruro estimulada por GABA. (...) De este modo se extenderán los hallazgos conductuales a la actividad del complejo supramolecular GABAa. c) En el paradigma residente-intruso se evaluará la generalización de la acción de Corticoesterona (CS) sobre el diferentes medidas conductuales de reactividad a un evento aversivo novel. (...) d) Se evaluarán los cambios en la actividad del sistema HHA en relación a las diferentes expresiones conductuales (sumisión, "boxing" o "freezing") asociadas a la confrontación social, para lo cual se determinará el curso temporal de secreción de CS y ACTH, antes y después del encuentro agonístico. (...) e) Se investigarán los efectos de una experiencia previa de derrota sobre la respuesta neuroendócrina inducida por exposición a un evento aversivo novel.

Aceleración de Algoritmos en Procesadores Multicore, GPGPU y FPGA. Algorithm Acceleration with Multicore, GPGPU and FPGA Processors.

El avance en la potencia de cómputo en nuestros días viene dado por la paralelización del procesamiento, dadas las características que disponen las nuevas arquitecturas de hardware. Utilizar convenientemente este hardware impacta en la aceleración de los algoritmos en ejecución (programas). Sin embargo, convertir de forma adecuada el algoritmo en su forma paralela es complejo, y a su vez, esta forma, es específica para cada tipo de hardware paralelo. En la actualidad los procesadores de uso general más comunes son los multicore, procesadores paralelos, también denominados Symmetric Multi-Processors (SMP). Hoy en día es difícil hallar un procesador para computadoras de escritorio que no tengan algún tipo de paralelismo del caracterizado por los SMP, siendo la tendencia de desarrollo, que cada día nos encontremos con procesadores con mayor numero de cores disponibles. Por otro lado, los dispositivos de procesamiento de video (Graphics Processor Units - GPU), a su vez, han ido desarrollando su potencia de cómputo por medio de disponer de múltiples unidades de procesamiento dentro de su composición electrónica, a tal punto que en la actualidad no es difícil encontrar placas de GPU con capacidad de 200 a 400 hilos de procesamiento paralelo. Estos procesadores son muy veloces y específicos para la tarea que fueron desarrollados, principalmente el procesamiento de video. Sin embargo, como este tipo de procesadores tiene muchos puntos en común con el procesamiento científico, estos dispositivos han ido reorientándose con el nombre de General Processing Graphics Processor Unit (GPGPU). A diferencia de los procesadores SMP señalados anteriormente, las GPGPU no son de propósito general y tienen sus complicaciones para uso general debido al límite en la cantidad de memoria que cada placa puede disponer y al tipo de procesamiento paralelo que debe realizar para poder ser productiva su utilización. Los dispositivos de lógica programable, FPGA, son dispositivos capaces de realizar grandes cantidades de operaciones en paralelo, por lo que pueden ser usados para la implementación de algoritmos específicos, aprovechando el paralelismo que estas ofrecen. Su inconveniente viene derivado de la complejidad para la programación y el testing del algoritmo instanciado en el dispositivo. Ante esta diversidad de procesadores paralelos, el objetivo de nuestro trabajo está enfocado en analizar las características especificas que cada uno de estos tienen, y su impacto en la estructura de los algoritmos para que su utilización pueda obtener rendimientos de procesamiento acordes al número de recursos utilizados y combinarlos de forma tal que su complementación sea benéfica. Específicamente, partiendo desde las características del hardware, determinar las propiedades que el algoritmo paralelo debe tener para poder ser acelerado. Las características de los algoritmos paralelos determinará a su vez cuál de estos nuevos tipos de hardware son los mas adecuados para su instanciación. En particular serán tenidos en cuenta el nivel de dependencia de datos, la necesidad de realizar sincronizaciones durante el procesamiento paralelo, el tamaño de datos a procesar y la complejidad de la programación paralela en cada tipo de hardware. Today´s advances in high-performance computing are driven by parallel processing capabilities of available hardware architectures. These architectures enable the acceleration of algorithms when thes ealgorithms are properly parallelized and exploit the specific processing power of the underneath architecture. Most current processors are targeted for general pruposes and integrate several processor cores on a single chip, resulting in what is known as a Symmetric Multiprocessing (SMP) unit. Nowadays even desktop computers make use of multicore processors. Meanwhile, the industry trend is to increase the number of integrated rocessor cores as technology matures. On the other hand, Graphics Processor Units (GPU), originally designed to handle only video processing, have emerged as interesting alternatives to implement algorithm acceleration. Current available GPUs are able to implement from 200 to 400 threads for parallel processing. Scientific computing can be implemented in these hardware thanks to the programability of new GPUs that have been denoted as General Processing Graphics Processor Units (GPGPU).However, GPGPU offer little memory with respect to that available for general-prupose processors; thus, the implementation of algorithms need to be addressed carefully. Finally, Field Programmable Gate Arrays (FPGA) are programmable devices which can implement hardware logic with low latency, high parallelism and deep pipelines. Thes devices can be used to implement specific algorithms that need to run at very high speeds. However, their programmability is harder that software approaches and debugging is typically time-consuming. In this context where several alternatives for speeding up algorithms are available, our work aims at determining the main features of thes architectures and developing the required know-how to accelerate algorithm execution on them. We look at identifying those algorithms that may fit better on a given architecture as well as compleme

Implementation of a unified userspace time handling library under the Linux OS

An appropriate assessment of end-to-end network performance presumes highly efficient time tracking and measurement with precise time control of the stopping and resuming of program operation. In this paper, a novel approach to solving the problems of highly efficient and precise time measurements on PC-platforms and on ARM-architectures is proposed. A new unified High Performance Timer and a corresponding software library offer a unified interface to the known time counters and automatically identify the fastest and most reliable time source, available in the user space of a computing system. The research is focused on developing an approach of unified time acquisition from the PC hardware and accordingly substituting the common way of getting the time value through Linux system calls. The presented approach provides a much faster means of obtaining the time values with a nanosecond precision than by using conventional means. Moreover, it is capable of handling the sequential time value, precise sleep functions and process resuming. This ability means the reduction of wasting computer resources during the execution of a sleeping process from 100% (busy-wait) to 1-1.5%, whereas the benefits of very accurate process resuming times on long waits are maintained.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Arquitectura wormhole per a una NoC 2D-Mesh

Aquest projecte presenta la implementació d'un disseny, i la seva posterior síntesi en una FPGA, d'una arquitectura de tipus wormhole packet switching per a una infraestructura de NetWork-On-Chip amb una topologia 2D-Mesh. Agafant un router circuit switching com a punt de partida, s'han especificat els mòduls en Verilog per tal d'obtenir l'arquitectura wormhole desitjada. Dissenyar la màquina de control per governar els flits que conformen els paquets dins la NoC,i afegir les cues a la sortida del router (outuput queuing) són els punts principals d'aquest treball. A més, com a punt final s'han comparat ambdues arquitectures de router en termes de costos en àrea i en memòria i se n’han obtingut diverses conclusions i resultats experimentals.