Structural, morphological, and magnetic characteristics of Cu-implanted nonpolar GaN films

Diluted magnetic nonpolar GaN:Cu films have been fabricated by implanting Cu ions into unintentionally doped nonpolar a-plane(1 1 (2) over bar 0) GaN films and a subsequent thermal annealing process. The structural, morphological and magnetic characteristics of the samples have been investigated by means of high-resolution X-ray diffraction (HRXRD), atomic force microscopy (AFM), and superconducting quantum interference device (SQUID). The sample shows a clear ferromagnetism behavior at room temperature. It is significantly shown that with a Cu concentration as low as 0.75% the sample exhibits a saturation magnetization about 0.65 mu(B)/Cu atom. Moreover, the possible origin of the ferromagnetism for the sample was also discussed briefly. (C) 2009 Elsevier B. V. All rights reserved.

Morphological defects and uniformity issues of 4H-SiC homoepitaxial layers grown on off-oriented (0001)Si faces

The morphological defects and uniformity of 4H-SiC epilayers grown by hot wall CVD at 1500 degrees C on off-oriented (0001) Si faces are characterized by atomic force microscope, Nomarski optical microscopy, and Micro-Raman spectroscopy. Typical morphological defects including triangular defects, wavy steps, round pits, and groove defects are observed in mirror-like SiC epilayers. The preparation of the substrate surface is necessary for the growth of high-quality 4H-SiC epitaxial layers with low-surface defect density under optimized growth conditions. (c) 2006 Elsevier Ltd. All rights reserved.

Influences of reactor pressure of GaN buffer layers on morphological evolution of GaN grown by MOCVD

The morphological evolution of GaN thin films grown on sapphire by metalorganic chemical vapor deposition was demonstrated to depend strongly on the growth pressure of GaN nucleation layer (NL). For the commonly used two-step growth process, a change in deposition pressure of NL greatly influences the growth mode and morphological evolution of the following GaN epitaxy. By means of atomic force microscopy and scanning electron microscope, it is shown that the initial density and the spacing of nucleation sites on the NL and subsequently the growth mode of FIT GaN epilayer may be directly controlled by tailoring the initial low temperature NL growth pressure. A mode is proposed to explain the TD reduction for NL grown at relatively high reactor pressure. (C) 2003 Elsevier B.V. All rights reserved.

Strain-induced morphological evolution and preferential interdiffusion in SiGe epitaxial film on Si(100) during high-temperature annealing

Strain relaxation in initially flat SiGe film on Si(1 0 0) during rapid thermal annealing is studied. The surface roughens after high-temperature annealing, which has been attributed to the intrinsic strain in the epilayers. It is interesting to find that high-temperature annealing also results in roughened interface, indicating the occurrence of preferential interdiffusion. It is suggested that the roughening at the surface makes the intrinsic strain in the epilayer as well as the substrate unequally distributed, causing preferential interdiffusion at the SiGe/Si interface during high-temperature annealing. (C) 1999 Elsevier Science B.V. All rights reserved.

High phosphorous doping and morphological evolution during Si growth by gas source molecular beam epitaxy (GSMBE)

Uniform and high phosphorous doping has been demonstrated during Si growth by GSMBE using disilane and phosphine. The p-n diodes, which consist of a n-Si layer and a p-SiGe layer grown on Si substrate, show a normal I-V characteristic. A roughening transition during P-doped Si growth is found. Ex situ SEM results show that thinner film is specular. When the film becomes thicker, there are small pits of different sizes randomly distributed on the flat surface. The average pit size increases, the pit density decreases, and the size distribution is narrower for even thicker film. No extended defects are found at the substrate interface or in the epilayer. Possible causes for the morphological evolution are discussed. (C) 1999 Elsevier Science B.V. All rights reserved.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

Morphological defects and uniformity issues of 4H-SiC homoepitaxial layers grown on off-oriented (0001)Si faces

The morphological defects and uniformity of 4H-SiC epilayers grown by hot wall CVD at 1500 degrees C on off-oriented (0001) Si faces are characterized by atomic force microscope, Nomarski optical microscopy, and Micro-Raman spectroscopy. Typical morphological defects including triangular defects, wavy steps, round pits, and groove defects are observed in mirror-like SiC epilayers. The preparation of the substrate surface is necessary for the growth of high-quality 4H-SiC epitaxial layers with low-surface defect density under optimized growth conditions. (c) 2006 Elsevier Ltd. All rights reserved.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Layered Architecture for Secure E-Commerce Applications

We present a layered architecture for secure e-commerce applications and protocols with fully automated dispute-resolution process, robust to communication failures and malicious faults. Our design is modular, with precise yet general-purpose interfaces and functionalities, and allows usage as an underlying secure service to different e-commerce, e-banking and other distributed systems. The interfaces support diverse, flexible and extensible payment scenarios and instruments, including direct buyer-seller payments as well as (the more common) indirect payments via payment service providers (e.g. banks). Our design is practical, efficient, and ensures reliability and security under realistic failure and delay conditions.